Hello everyone, I'm the Leviathan from the LibreSilicon project. In this video I will explain to you how to actually make use of the LibreSilicon manufacturing process standard and how to scale it from a small laboratory configuration up to industrial mass scale manufacturing levels.

The main difference between an industrial scale manufacturing machine and a laboratory setup is that an industrial scale machine has the capability of loading batches of silicon wafers at once,

which are provided to that machine in cassettes as depicted here in the slides on the left. While in a normal laboratory setup you usually only load one wafer at a time using a pair of tweezers.

The reason for the bulkiness of most of the industrial level machines is exactly the required mechanics to perform all this batch loading and unloading into anti-receiving wafer cassettes. The biggest problem if you have ever tried to manufacture some semiconductor prototypes with a foundry

is that there is a minimum quantity you have to buy before they even start talking to you. In addition to that they make you go through a load of NDAs in order to even give you basic information

on how to start designing your circuit with the highly proprietary and secret manufacturing process. In addition for getting a foundry to even talk to you, and not a really really big problem, is that as soon as you have designed a chip and tested, you've burned through hundreds of thousands of US dollars

to have a feasible working sellable product, which can only be manufactured with that specific foundry.

As soon as this foundry goes out of commission, may it be natural causes, earthquakes or bankruptcy, you are screwed. You have to go through the entire prototyping, development, R&D again to adapt your design to another foundry, which costs you yet another 100,000 US dollars or more.

This is also a really significant reason why I decided to start LibraSilicon, in order to introduce a semiconductor manufacturing process standard, which allows portability,

to a certain degree at least, between multiple foundries and laboratories. My goal is not to convince large already established manufacturers to adapt the LibraSilicon process standard, but to take the power out of the hands of those very same and put all those secret manufacturing recipes

into a public open source domain, allowing small startups to form and fairly compete in a free and open market, because that's how a free market capitalism is supposed to work.

Large corporate entities with government funding, under government control, they do not care about transparency issues in semiconductors, because they are perfectly fine, because the government profits from the possibility to put spy vectors into chips,

into the products of their pet companies they are running. Those big companies funded by government, by taxpayer money, money extorted from people, that's the lucrative merger between state and enterprises,

or as this one funny Italian guy coined it, corporatism, of which he was super proud, because it was an important part of his new societal order he just had come up with, the word for a bundle of sticks in Italian.

By the way, the idea behind this project is to uncease the means of production, which are right now in the majority in the hands of the government. I want to make it impossible in the future for anyone to use intellectual property laws

to wage lawfare against other countries and their economy, like it happened in 2019, when the US administration back then forced Synopsys to cancel the licenses they had granted to Huawei.

This is an unacceptable situation, that most of the broadband IP cores, which are needed to build a halfway modern smartphone or any other telecommunication device, are in the hands of a few government controlled entities. This has to stop.

In short, Libris Silicon aims to give you everything you need to get started, to get your own little startup off the ground, at least from the know-how perspective, maybe chemical recipes or ideas how to design the process flow,

how the safety manuals on chemicals, how to use certain machines. It's a collection, a knowledge database, if you want, on how to make a working CMOS chip or add a flash chip,

because in my design I also have Sonos flash, silicon oxide, nitride oxide, silicon. This all collected in one place where you can find answers to your questions.

How do I build this? And since I'm an ANCAP, I figured I'll also make a print version of it at some point. It's fitting the anarchist semiconductor cookbook. And yeah, it started as a joke, but I guess it's really something worth thinking about.

I mean, having a print book. Here a picture of a body of mine, Victor Lee, and me working together in the clean room at Hong Kong University of Science and Technology.

I assume you already know how transistors work since you're watching a talk about how to manufacture transistors. This slide is only for refreshing your memories.

Let's say we have here a transistor with a gate source drain. Only difference between an NMOS and FAT is that in a NFAT configuration, the bulk, or also known as the body, of the transistor is tied to the source, which shows one of the two integrated diodes which are naturally occurring due to the PN junction in the transistor.

And so you get the three integrated freewheeling diode in an NFAT. So, if you put the voltage here between the gate and the source,

what happens is that you basically have an electric field charging the capacitor, pushing electrons into the P-doped material, and due to recombination, you start opening a channel.

First, the recombination leads just to the change from P-doped to neutral silicon, and the higher the voltage becomes, the further you overcome the required band gap energy

to turn the P-doped silicon into virtual N-doped silicon, and that creates here a channel between the two N-doped zones, which is also virtually temporarily N-doped.

That's why NMOS and NFAT are also known as N-channel transistors. This is only temporary, of course, unless you put too much voltage into it, then the black magic smoke comes out of the pot, and it's permanently conducting, which in the business we introduce call also broken.

This is an N-channel, also here. N-channel, same thing. The more voltage, the higher the conductivity between N-plus through source and drain.

As you can see here, in an NMOS, from an engineering perspective, source and drain are interchangeable. NFAT, however, because one of the two junctions is being tied to the bulk, there you actually have to take care about the polarity of the transistor.

In practice, source and drain also in NMOS manufacturing can vary, depending on what purpose this NMOS has been made for, so you should really follow the pin assignments in the datasheet when designing your circuitry.

Values from the datasheet, like the drain source resistance, the capacities between those drain source gate pins,

they are influenced by not only the gate oxide thickness, or the bonding wire resistance, or the width of the channel, but also by manufacturing specific factors in the actual transistor and its interconnects on the die,

into which I will go in the following slides. While building standalone transistors can be achieved with relatively simple equipment, as soon as you want to start to integrate transistors into something more useful,

like into logic gates or even further into processors, you need to start isolating logic gates from each other in order to prevent latch-up effects. It doesn't matter whether you perform a very large silicon integration,

or VLSI for short, which works down to 500 nanometers or 350 nanometers, which can still be isolated using LOCOS, or whether you are doing ULSI, ultra-large silicon integration,

which is needed for very, very small feature sizes, like 24 nanometers, 65 nanometers, where LOCOS doesn't work anymore, and you have to use STI, shallow trench isolation, you will always have to compensate for the change in topology by using planarization.

More specifically, chemical mechanical planarization, also known simply as polishing, in which where you take the wafer with the oxide, with the bumps,

and basically sandpaper away the bumps. In order to avoid irreversible crystal damage on your silicon wafer, or with the metal interconnects, damage to the wires, you have to use a layer of protective silicon nitride, which serves as an endstop for the polisher,

by making use of the fact that the selectivity from low temperature oxide to nitride is between 100 to 1 and 1000 to 1, depending on the density of that said oxide. The drawback from nitride is that it has a very high dielectric constant,

which in turn increases the capacity between the metal layers. As you can see here in those pictures, on the left, there is an implementation which escapes the planarization step

between the metal depositions. As you can see, anything more complicated than a single metal interconnect layer becomes unfeasible without polishing steps in between. On the right, you see an implementation using planarization in between the interconnect steps,

which gives us a really nice interconnect structure without hardly any connectivity issues. When performing a CMP step, the CMP endstop nitride layer must never be omitted.

Failure to apply a nitride CMP endstop before depositing the oxide will lead to damaged structures. It's important to note that you also have to take into account edge effects on wafers.

The planarization will never be 100% even, but more in a concave shape, because the force distribution from the center towards the edge goes down towards the edge. So you have to calculate enough thick nitride and enough oxide

to have an even distribution with tolerance ranges, so that you can compensate for the edge effects. Those edge effects exist always, but the bigger the wafer, the more even the distribution. This means with bigger wafers, you have a higher yield,

because the area in which you polish away the exact right amount is higher, the bigger the wafer. This is the reason why in the industry there is a push towards bigger and bigger substrate wafers. The process itself is pretty simple. First you apply a petoxide so that the nitride sticks,

then you apply the nitride and on top of that you apply the isolation oxide. Then you polish it away. In order to have proper metal interconnect without any broken wires,

I highly suggest following somehow along the lines of the process design I made for the HKUST laboratory. As you can see here, before etching the wires touching down to the transistor,

I first deposited an adhesion layer for the nitride protective layer, the CMPN stop, the so called petoxide, which makes sure that the nitride nicely adheres to all the different materials.

Then I deposited plenty of oxide, in this case 1 micron, because it's a 1 micron feature size we have been producing. And then after polishing, depositing photoresist, exposing, developing and etching the contacts.

Then in the next step where the metal layers deposited. In our case we were using silicide thin film layers in order to reduce the sheet resistance of our transistor junctions.

Because you cannot directly contact with aluminum onto silicide, because aluminum atoms would travel into the silicide and would increase the resistance of the silicide, I had to introduce a nickel diffusion barrier between the aluminum and the silicide.

Adding a nickel finish between every aluminum layer has the nice side effect that the aluminum wires do not oxidize during handling.

Since I already touched on how CMPN works, namely being some kind of sandpapering on a micro scale, I'll go a little bit more into detail here and explain to you with some example how CMPN works and how it actually looks like in practice.

So what you have is the wafer carrier holding a wafer towards the surface with some polishing pad. On this polishing pad you dispense a solution in which nanoparticles are being dissolved,

like for instance Zeria industrial ceramic. Then you apply a well defined pressure which you set in the control panel of the CMP machine. Here on the right is a picture of a very affordable laboratory level CMP machine,

which you can find online on Alibaba for instance. There is no problem in case you want to start a startup and start manufacturing chips, to just settle for this really affordable small one until you can afford an upgrade.

Here a little example of a CMP machine and how it's being used. This is the only pole I showed you in the slides and that's basically a demo video. So you can see first of all the mat is being fixed and now the slurry, the liquid with the industrial ceramic nanoparticles is being put onto this mat.

Then a holder with the wafer samples downward is being put on and screwed in and the rotation speed is being set in the interface. The rate can be calculated based on test wafers which have been fed through first and measured.

Here is an entire wafer being polished with the special setup.

Same thing, you span it in, set the rotation speed, set the pressure on the holder and then you let it run. Silicon is called a semiconductor because it isn't really a good conductor,

neither is it really a good isolator. Only when you dope it, it will start conducting well. You have the choice to either use more electrons, so elements which have a higher electron number in the shell than silicon or you can use so called holes by doping it with an element which has a lower electron number in the shell than silicon.

This causes those before mentioned p and n junctions. You have actually three methods how you can introduce additional elements into a mono crystalline or polycrystalline silicon lattice

either through diffusion with a gas or with pre-deposition using liquid deposition with a spin coater or you can use an ion implant.

Pre-deposition with a dopant gas is not so different to pre-depositing those dopants by dissolving them in a liquid and pre-depositing them on the wafer by using a spin coater. There is only a few additional steps which make it worth considering as an alternative to using boron gas

because boron gas is regulated and might pose problems during acquisition as a small startup which doesn't have all the licenses yet. For diffusion and pre-deposition with a liquid dopant you typically use a tube furnace like depicted here as a schematic

where you have a tube typically made from quartz glass, highly temperature resistant in a box. Inside the box you have heating elements which heat the quartz tube up from the center to what's outside which causes thermal zones.

Typically in the middle of the box you have the desired temperature range you set in a configuration of the tube furnace. The silicon wafers are put into little glass bolts, holders with slits in which you put the wafer in like those old school CD-ROM holders.

This quartz glass bolt is made from the same material as the quartz tube in the furnace and can survive those very high temperatures.

After positioning those wafers in the glass bolt, the glass bolt is then placed in the tube and shoved approximately into the center where the thermal zone with the desired heat range is located.

There are big versions of those tube furnaces. The industrial scale can be seen on the left here in the slides while a small low cost laboratory variant can be seen on the right in those slides.

Both however work the exact same way, just the scales differ. One thing to note about those furnaces is that you have the possibility to flush the tube with inert gas like nitrogen in order to avoid reactions when not desired which would happen if your material would be reacting in a high temperature with oxygen from the atmosphere.

The before mentioned ion implantation is being performed with really ginormous particle accelerators which could stem from some James Bond movie and thought of by some insane Bond villain.

They are a reality used in industrial setups. However, small startup foundries most likely cannot afford to buy such a machine so I will not go further into detail. The main problem we have at LibreSilicon is the chemical vapor deposition step because most

gas is needed for recipes for things like polysilicon which is required to form polysilicon gates. All for depositing the low temperature oxide require the lane gas SiH4 which is

strictly regulated and has been used in World War II as a nerve agent. It might pose a real problem to get the licenses needed to acquire such gases. We here at LibreSilicon work on developing alternative recipes which can achieve the same results,

silicon nitride, polysilicon and silicon oxide formation without the need for highly poisonous and regulated gas. For depositing metals which are required for the metal interconnects or also for depositing metal which can be

reacted in an RTP furnace in order to form silicide, a sputtering machine is probably the easiest solution. A sputter in general is basically permanent magnets which in conjunction with a sputtering target,

the desired material which is supposed to be deposited on the sample as a thin film. The material and the magnets together form a magnetron like the one you are used to from your microwave oven in your kitchen.

In a low pressure atmosphere, the plasma ejected from the metal is travelling through the low pressure atmosphere to the substrate due to an electric field thanks to the power supply. Everyone who ever accidentally or by purpose has put the piece of metal into the microwave oven knows this effect.

Those sparks, that's plasma. In those lights on the left you can see a typical industrial large sputter while on the right

you can see a low cost laboratory friendly variant which is available on Alibaba and other Chinese supplier websites. Here you can see a plasma discharge from a self-made sputter. Credits go to the channel Applied Science on YouTube.

When it comes to etching the microstructure on your wafer, you have two options. Either you go the wet etching route or you can spend a little bit more money and go the dry etching route with a plasma etcher.

For wet etching there is a few common recipes, chemicals used for certain materials. For instance hydrofluoric acid for etching silicon oxide, metals, TMAH for etching silicon and polysilicon, KOH for the same purpose as TMAH,

Piranha solution which is hydrogen peroxide and sulfuric acid and water. That is being used in case you want to perform silicide formation. That has delivered the best results in the laboratory to clean away unreacted metal after the silicide formation from the wafer.

And H3PO4 for etching silicon nitride. The disadvantage of wet etching is that it is highly isotropic etching while dry etching produces much better and sharper results.

Also with dry etching you have a better control over the depth and the etch rate. In general when you etch you have to keep in mind that the bigger the attack area of the acid the higher the etch rate. This is the reason for design rules which define the size of a via in order to have better control over and under etch.

In this slide you see the difference isotropic etching on the left which etches further horizontally as it etches down. So you will have an etch further than the mask.

While with dry etching you have a nicely vertical etch down and virtually no horizontal etching. It is important to note that all the chemicals I listed before for wet etching are highly poisonous and super duper deadly when handled wrong.

So just to be sure and to make sure that you cannot sue me in case you die from handling those chemicals. I now tell you to wear a PPE. It is not a political statement trust me. It is just really take precautions so that you don't get poisoned.

Also little piece of advice look at the poison data sheet of each of the chemicals and maybe dilute those chemicals to a degree where a single drop won't just kill you immediately. It is anyway better to have diluted etchings because the slower the etch rate the better the depth control.

In case you really don't know how to properly handle poisonous chemicals ask someone who knows. Maybe not the obnoxious neighborhood Karen who wears a PPE when she is going to buy groceries.

Ask someone who really knows what they are doing. But if you are unsure and you don't feel 100% confident handling those chemicals please don't be ashamed to ask for advice. For wet etching you can either go professional with a big wet station like here on the slides on the left.

Or you can go like small scale laboratory like with this little mini home wet station from a Jerry Ellsworth uses in her video cooking with Jerry making microchips at home. Or you can actually also use Tupperware to have your chemicals in there.

Just as mentioned before make sure that it is sufficiently diluted. Don't put food into containers where you have stored poisonous chemicals. Keep the stuff separated. Don't drink it. Don't put it into your eyes. Common sense. Dry etching also known as plasma etching can be described as sort of an inverse sputtering because it is a similar principle.

In a low pressure atmosphere etching gas chemical mix is being flushed into the low pressure chamber.

And then agitated by an RF setup which bombards the target and removes the atoms from the target atom by atom. So that's a schematic of the thing. You have coils which agitate the gas and turn it into a plasma which then bombards the sample you want to etch.

And all the areas which are not protected by a photoresist layer are being removed atom by atom.

Here is an example. On the left you see an industrial scale dry etching machine as it is being used in factories. On the right you see a low cost laboratory variant.

As mentioned in order to etch those structures we of course need to first somehow transfer those images we designed in our layout tools onto the wafer. For that purpose we use something called photolithography in its principle the same as developing a photograph.

You have a photo active resist which is being deposited onto a wafer using spin coating. And after that you use UV light which you focus and beam through a mask of some sort on which your pattern is being painted on.

Then this pattern is being focused again and being projected onto the photoresist which chemically reacts in the areas where UV light hits the resist. And after development your structures have been transferred onto the wafer.

Typically in industrial setups you use something like a big stepper unit which takes cassettes full of wafers. As mentioned in the beginning batch loads those wafers. And the patterns are being laser printed onto a glass plate which is coated with a metal of some sort.

On the right you see a mask with four of the layers for our Libra silicon test wafer. This is one of the masks from the mask set we used in HQST to test Libra silicon with the recruitment.

The stepper liner then takes those patterns from those masks and scales them down in size and repeatedly exposes the same pattern onto the wafer one next to each other.

The result is this tile pattern you see on this wafer. This is the repeated same pattern exposed over and over again by the stepper. The result you can see here, that's transistors we did for the Libra silicon project.

Those are special transistor test structures to characterize our process. And on the very right you see those little specks on the wafer, that's dust. The problem with mask lithography is that mask making is very expensive.

So for a laboratory set up it makes sense to have a maskless stepper aligner which uses a DMD display that's a micro mirror device. It's the same type of technology used in projectors for home cinema. As a matter of fact Sam Selove did build his own maskless stepper aligner hooking up a projector to a microscope.

We at Libra silicon are right now working on a maskless stepper aligner design inspired by Sam Selove's design. Just that our design will be more integrated and with parts which can be reordered easily.

Here you can see a spin coater in action. Credits go to Holography Homelab. I assume they mean Holography Homelab.

It's spelled way like here in the white text. Holography Homelab. In case you wanna go check them out. The specs in our test structures which I mentioned in the last slides can be really really impactful when your microstructures shrink in size.

Here you have an overview about different types of particles floating through the air at any given time in a non-clean room environment.

For instance a scale, the thing your body loses all the time, is around 10 microns. Same goes for a hair, the diameter, a little bit more than 10 microns.

Pieces of insects floating around, let's say 100 microns. Then we have here starch. Here the scale 1 micron, so that thing is also around 100 microns in diameter.

A wood particle, 100 microns. A pollen, 50 microns. Then fungal spores, 30 microns. You get the idea. You have to get that stuff out of the air you're working with your microstructures.

If you have 10 millimeters transistors or so, it's not a big problem. 50 microns, you already cannot get anything working out of your manufacturing attempts if you have mold in your garage.

So you have to make sure that the air is somewhat clean. The smaller the structures, the more impactful particles floating in the air. So you should really think about some contamination control measures in the area you are working.

Because if you have like a 1 micron node, try to make 1 micron transistors or 500 nanometers and you have like 10 micron particles.

That's basically like an asteroid crashing into your integrated circuits. So if you really want to go high-tech, sub-micron, 500 nanometers or less, you should really wear proper cleanroom garment in a cleanroom environment.

Wear latex gloves and surgical mask. And again, that's not a political statement, but if you don't do that, your circuits will just not work. Upside, due to the current crisis, surgical masks and gloves are super inexpensive at the moment.

A box with cleanroom, with gloves, gloves, awesome. A whole box, I think 100 gloves for like 10 euros. Reduced price, really awesome. So I have enough gloves to work with chips.

Also surgical masks, super cheap. Now we only have to gaslight people into thinking that they can slow the spread by wearing bunny suits. Because those are still super expensive. When it comes to cleanroom environment, you either can go hardcore professional with a

big, big cleanroom with laminar flow all through the room in a bunny suit. Those people, by the way, were not really doing wrong. They're not wearing masks. Again, not a political statement, just a point about contamination control.

You see the light here is yellow. Yellow light is typically used for photolithography areas in a laboratory because the photoresists are made in a fashion that are not reactive to yellow light.

In a cleanroom, you typically have two circulatory systems. One system pumps the air which is already in the room through multiple stages of paper filters, pumps it back through the ceiling, blowing all the dust towards the floor,

where the air is either sucked in sideways or in some instances through perforated floorboards in the bottom of the room. Then you have a second pump system which pumps fresh air in, filtrates this air through multiple filters from the first biggest particles,

and then the hyper rays increase until you have fresh air so that you don't suffocate in the cleanroom, which has been filtrated to the cleanroom level degree required for the work environment.

There is also the possibility to refurbish used shipping containers in case you do not want to build a factory building. Or you can have your cleanroom environment in a glove box form factor, where you don't even have to wear a cleanroom suit and other protective gear,

because between you and your samples is the gloves of the glove box. The conclusion from those explanations is that you certainly will need a furnace for the CVD and diffusion steps.

You will need a spotter in order to deposit metal for the interconnects. You need a wet station to clean your wafer in between the steps. You need a PPE so that you don't accidentally poison yourself or at least reduce the risk that you accidentally poison yourself.

You need a lithography system of some kind to transfer the patterns from your computer to your wafer. You need a microscope to check whether the structures turned out the way they are supposed to.

You need some way to keep the gigantic particles away from your microstructures. Good to have, in case you want to do anything more complicated than one micron structures with one single metal interconnect layer,

would be a CMP machine and if you want to go sub-micron you totally need a dry etcher. Optionally, in case you want to do something like annealing titanium on top of silicon in order to produce titanium silicide, in order to reduce the sheet resistance of your transistors, you will need a rapid thermal processing furnace.

And if you have some bitcoins left on your wallet, you can also buy an ion implanter. Now that I've been talking so much about the manufacturing side of things, let

me tell you that LibreSilicon is not only how to manufacture the actual physical chips, but we also work on the software side and the design tool side. The LibreSilicon PDK contains, among other things, the design rules, which are

a direct result of the limitations of the machines and auto-process parameters. We also provide a collection of cores, which you can use in your layouts, like analog digital converters and digital analog converters, flash cells and RAM.

Also basic components like resistors, diodes, guides how to build inductors if you have the possibility to use iron in the process. You can also build inductors.

And then we have the EDA tools. You can either use Qflow, which includes magic, graywolf, qrouter and yours. Or you can use OpenLane, which is a concurrent project, but we cooperate with them. Under pdk-libresilicon.com you can have a test run of our standard cell

generator, which generates standard logic cells based on design rules you provide to that tool. The tool itself, of course, is LibreSilicon, is open source and can be downloaded from GitHub.

Our team has public weekly mumble sessions. Every Sunday, 1800 Zulu, so 6 p.m. UTC, on mumble-libresilicon.com. We also have a mailing list, and if you're really in dire straits, you can drop me a direct email to my email address here.

Because I'm not a friend of getting government funding, because I'm not a fan of using money which has been extorted by the government from homeless, hardworking people in form of taxes,

I would appreciate donations on this dedicated Bitcoin wallet for this talk. I would have a much better feeling if I knew that the money I'm using for this project has been given voluntarily to me.

Thanks for watching.

And inspiring talk. I hope the presenter can go back here in the room for live questions and answering any questions that came up on the chat.

Just wait a bit. He'll be here soon. Well, thanks again. This was an excellent talk and very inspiring.

And feel free to answer any questions. Okay. Totally. I already, during the streaming, I answered some highlights that people asked me. So one thing is how much would the initial investment cost? Someone asked.

And that's why I showed all the small machines next to the big ones, right? The small machines, they're kind of, well, they're affordable. They're more affordable than the giant ones. But for instance, the furnace is still like $3,000 at least.

And like a natural plasma etcher is also in the ballpark $10,000, $6,000, $10,000 US dollars. So every machine, basically every machine for the different steps, you have to count like $10,000 US dollars.

Now I've shown you the least in the talk, what equipment you need. Except the ion implanter, which is super expensive. But for all the machines, you can just like, that's $10,000, that's $10,000, that's $10,000.

So ballpark number is like, you know, let's use a stable currency. It's around, I estimate like three or four bitcoins to build a factory, a small factory, garage factory.

Because as I mentioned, you also have to make sure that you do not only need equipment, you also need some clean room environment to put it in there. And I checked with shipping container suppliers who sell second hand, you know, used up shipping containers.

Because one business case I start, because there is a laboratory in Portugal interested in expanding the clean room that they have close by. And so I checked for, well, it's a business case, right?

So check for containers and it's around like $2,500 US dollars at least for a very simple container. And that's also money you first have to get. It's like $2,000 US dollars for shipping container. Then you're not done, then you have the shipping container.

Then you need to adapt it to be a clean room environment, right? So yeah, so it's not cheap to build a microfib. So it's not something you just do quickly in your garage, right? But it's certainly, especially with Libra Silicon as a starting point, it becomes only very

reasonable to consider starting a startup, getting together, getting some funding and starting your manufacturing.

Let's see, we got questions here. That's cool because I also have, let's see what they ask in the VLSI chat. So I just get positive feedback, so not really, well, I'm glad the talk was informative.

Maybe the thing is I have three screens and the GoPro is here. So now I look at you and the GoPro. OK, I'm glad it was informative.

So, yeah, if someone's interested into starting a microfib and wants me on board, let's do this. I mean, I've been to it. I've been talking to some guys from Liboland recently because they applied for citizenship.

So there are some people who are interested. So that's actually, yes, I'd totally be open if you want to join a joint venture. And to start the fap, text me, email me, you have my email.

Right. So, yeah. And as I said, everything like the process flow is open source. It's supposed to be a standard. So it's not like like with all the companies where all your R&D results are being locked away in a safe for the rest of eternity.

Like we share with the community. And as I said in the video, maybe even as a print book. Well, that will be great.

So there are two highlights here. So thank you from Nathan. You're welcome. Then a puzzle boom says putting everything in the container is a bad habit of software.

OK. You know, it's the advantage of having it in the container is that you can actually it's more to lower the factory. It suddenly becomes more to lower. So especially if you have like a closable airlocks, you know, like the detachable airlocks,

you can basically expand, extend or scale down your factory space, depending on the space required.

Or you can do ad hoc upgrades of factory areas. You don't have to have construction sites because keep in mind, you do non manufacturing or micro scale manufacturing. That means you cannot go in. Well, you can, but you fuck up your production. If you go close to your factory and then have a check hammer there because there's vibrations in the floor.

Right. So it's easier to actually have your factory space in modular containers, which you modify beforehand somewhere else where you can have as many vibrations while doing your construction and then ship the container there.

Put it connected to the rest of the containers and you have your factory expanded. So, yeah, it's it's actually a hot plug in the hot plug. You know, like with RAM hot plugging that you care that there are some other boards which support the feature of adding RAM

by the system is rooted and having your factory set up with shipping containers basically allows to do something like that for your factory. Where you actually can expand factory space while you're in production.

So, yeah, I went a little bit off rail there, I guess. Okay, I think we'll have time for one quick question answer and then we may have go to the hallway. Okay. Okay. That's another one concerning machines. What about the lithography on the flow chart

you have shown it has the ASML stepper but this is a seven digit investment. Oh, yes, that's the ASML stepper is the one we use at HKUST. But I said that we are working on them on the maskless lithography system

right and that that design will include the DMT or the digital micro mirror device. It will be basically the same approach Samsung has just that our design will be more integrated.

So the problem here is that Texas Instruments, their DMT chips which are specified for the UV range of light.

Those are expensive like in the thousand bucks range ballpark number thousand US dollars ish per chip, which makes well prototyping usually with such the it's an expensive chip. So we have a real problem there.

Well, alignment is alignment strategies that would blow the scope of this Q&A right now. Let's just say we have some alignment strategies we're working on it right now.

It's work in progress. So, but we're developing right now.