Coriolis RTL-to-GDSII Toolchain
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00:00
Duality (mathematics)Demo (music)Information securityDataflowPresentation of a groupDomain nameSource codeCartesian coordinate systemEnterprise architectureComputer hardwareSoftwareMultiplication signSuite (music)CoprocessorInformation securityPower (physics)Software architectureExistenceProjective planeContext awarenessIndependence (probability theory)SpeichermodellPlanningFuzzy logicShared memoryPersonal digital assistantProcess (computing)Prisoner's dilemmaNP-hardGame controllerComplex (psychology)XMLComputer animation
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Field programmable gate arrayRouting2 (number)Point (geometry)Data structureDifferent (Kate Ryan album)Factory (trading post)Figurate numberInformationDataflowLogic synthesisRight angleMatrix (mathematics)CAN busFamilyAreaTendonView (database)Product (business)PRINCE2Data storage deviceFood energyState of matterThermal expansion1 (number)CausalityProgram flowchart
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Logic synthesisSicFLOPSDataflowElectric generatorLogicParameter (computer programming)Rule of inferencePoint (geometry)Set (mathematics)Logic synthesisComplex (psychology)Process (computing)Topologischer RaumFreewareProjective planeRouter (computing)LogicLogic gateSoftware development kitOpen setView (database)Translation (relic)BitMereologySubsetSlide rulePhysical systemComputer fileNichtlineares GleichungssystemValidity (statistics)Boolean algebraDataflowFormal verificationTerm (mathematics)Virtual machineDescriptive statisticsData structureConnectivity (graph theory)Axiom of choiceVery-large-scale integrationFunctional (mathematics)Finite setConnected spaceDifferent (Kate Ryan album)Identity managementCoefficient of determinationProduct (business)Observational studyMusical ensembleVideoconferencingDegree (graph theory)Service (economics)Pattern recognitionGreatest elementWhiteboardWebsiteSingle-precision floating-point formatSinc functionMultiplication signGoogolSimulationPlanningArmComputer animation
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Parameter (computer programming)Dijkstra's algorithmRouter (computing)ArchitectureLogic synthesisNetwork topologyInsertion lossCore dumpMenu (computing)Static random-access memoryRaw image formatGoogolMathematical optimizationMultiplication signDigital electronicsMereologyImplementationÜberlastkontrolleMetreAlgorithmOpen setAreaMixed realityMicrocontrollerData structureSpacetimeTask (computing)Mathematical analysisLoop (music)Router (computing)Connected spaceTerm (mathematics)Level (video gaming)Constraint (mathematics)Fluid staticsNeuroinformatikNumberKey (cryptography)Scripting languageReal numberTelecommunicationElectric generatorLogic gateFeedbackPropagatorDampingBinary codeArithmetic meanDatabaseShape (magazine)GoogolRoutingNetwork topologyFrequencyInterface (computing)Electronic visual displaySelf-organizationPhysical systemRaw image formatBlock (periodic table)Projective planeSystem call19 (number)Point (geometry)Square numberMeasurementArmBlogDataflowCASE <Informatik>Computer programmingGodInteractive televisionGraph coloringParameter (computer programming)Labour Party (Malta)Order (biology)Moment (mathematics)Sign (mathematics)Service (economics)Functional (mathematics)Special unitary groupMarginal distributionSheaf (mathematics)Game theoryThomas BayesComputer animationProgram flowchart
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Error messageArithmetic logic unitPlug-in (computing)Block (periodic table)Alpha (investment)Function (mathematics)Text editorInformationGastropod shellDirectory serviceData modelElectronic visual displayLevel (video gaming)CodeRead-only memoryDevice driverAnalogyComputer fileBuildingNetwork topologyLinear mapInformation systemsMeasurementFinite element methodCore dumpDigital filterPattern languageSynchronizationChi-squared distributionScripting languageRoutingAlgorithmLogic synthesisCoprocessorWeightComputer fileComputer programmingZoom lensRepresentation (politics)Function (mathematics)DistanceNetwork topologyECosVideoconferencingState of matterArithmetic progressionCASE <Informatik>GravitationSign (mathematics)WebsiteReading (process)Cheat <Computerspiel>Computer animation
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Block (periodic table)RoutingLevel (video gaming)Element (mathematics)IterationComputer fileAnalogyDevice driverBuildingCommitment schemeInternetworkingLine (geometry)WeightCoroutineZoom lensRadical (chemistry)Computer animation
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MeasurementLevel (video gaming)Core dumpAbstract syntax treeDatabaseAnalogyComputer fileBlock (periodic table)Line (geometry)CoroutineGoodness of fitGame theoryGoogolWebsiteComputer programmingVertex (graph theory)Computer animation
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RoutingMultiplication signGroup actionMechanism designStaff (military)Theory of relativityDistanceCASE <Informatik>InformationLevel (video gaming)FamilyHydraulic jumpParameter (computer programming)ResultantRule of inferenceCAN busQuicksortMereologyLabour Party (Malta)SimulationSet (mathematics)Power (physics)Automatic differentiationInformation securityChaos (cosmogony)Endliche ModelltheorieObservational studyNumberDatabaseHeat transferTransportation theory (mathematics)Water vaporTemplate (C++)Type theoryComputer programmingInteractive televisionEquivalence relationFluid staticsOnline chatMixed realityTask (computing)Logic gateLogicMoment (mathematics)Computer animation
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RoutingOpen setLink (knot theory)Revision controlMereologyInstallation artComputer fileMultiplication signProjective planeLabour Party (Malta)Dynamic random-access memoryRepository (publishing)FreewareVolume (thermodynamics)SoftwareOnline chatGeometryLibrary (computing)Scripting languageAutomationProcedural programmingSemiconductor memoryCodeProcess (computing)Bit rateProduct (business)Network topologyUniverse (mathematics)Connected spaceVotingWeightData storage deviceMetreForm (programming)CASE <Informatik>Message passingForcing (mathematics)SequenceType theoryFamilyWater vaporTerm (mathematics)Hydraulic jumpService (economics)Computer animation
48:31
Computer animation
Transcript: English(auto-generated)
00:09
Hello everyone and welcome to this presentation of the Coriolis ASIC design flow. The presentation is organized as follows. First, I will remember the reasons that are behind or driving us to make Coriolis.
00:27
Then I will present the basics of making an ASIC, that is, how ASICs are done, which will lead me to introduce the design flow with a special emphasis towards software architecture.
00:46
Then I will summarize the improvements that we made in 2021 and go to the plans for 2022. And finally, I will present a small demonstration about the latest capabilities of Coriolis.
01:11
One of the first reasons we started to develop Coriolis was to provide academics with tools
01:20
independent from commercial software which have closed source and with which you cannot exactly control what you do or being trapped by backward capabilities problems. So with our tools, you know exactly what's going on inside the source and moreover,
01:46
if it doesn't exactly suits you, you can modify them. The second advantage is that with the software, you can publish and share and modify
02:04
the hardware design you have made. This avoid to have to reinvent the wheel every time you want something that has been already been done by others but cannot be published. We hope to build a free community
02:28
with that approach, exactly like the free software made for Unix. But aside from those academic aspects, we also wanted Coriolis to be able to handle
02:43
real situation designs so small and medium enterprises will be able to make, at a low or no cost, small or medium designs without having to pay the huge fees
03:03
usually associated with commercial software. Of course, by being open, we should bolster the securities. As I remind you, a secure software cannot run in an insecure hardware.
03:23
If your hardware is not trusted, there is no way you can make a trusted software upon it or at least that I'm aware of. Another aspect of this project is that
03:41
it will help ensure the continued existence of the hardware. Typically, there are some applications or domains when you want to be able to provide a design for a very long time. Typically, imagine a nuclear power plant
04:06
which has been qualified with a certain processor or certain kind of hardware. It will be only qualified for those hardware and not others. So you have to be able to provide
04:21
those exact same hardware for the lifespan of the nuclear power plant, which may be 50 or maybe even 60 years. So imagine a processor that has that kind of lifespan. As of today, I don't know any one of them. So we wanted to start small and our first targets are the mature
04:53
node, that is the node not lower than 130 nanometers because the problem to solve
05:01
are less complex and we can make demonstrations and still have useful designs. I assume that most of you are familiar with the FPGA design flow and not with the ASIC design flow.
05:25
So this figure helps to understand the difference. On the left-hand side, you have the FPGA design flow which starts by a logical synthesis, then a place and route upon the FPGA matrix to targets.
05:41
That place and route generates a bitstream that you send inside the FPGA that you upload onto the FPGA and which configures it. Note that the FPGA is itself a kind of ASIC. It's a finished ASIC but it's an ASIC. On the other side, on the right side, you have the
06:03
ASIC design flow which starts the same by a logical synthesis but on a slightly quite different structure which is the standard cells and gives a netlist. Then we perform the physical synthesis which is called the place and route and gives us a layout. The layout is a
06:26
drawing, just a big drawing, and this is this drawing that we send to the fundry. The fundry is the factory that will translate, transform your design, your drawing,
06:44
your layout, into an ASIC and it will send back you that ASIC. There are two blocking points until recently in this design flow. The first point is the EDA tools. EDA tools exist but the commercial one comes with a very high license fee.
07:08
For example, I heard that to benefit from the full flow of one major vendor, it's above a million euros per year. So that's quite as expensive for a small or medium business.
07:26
The second blockage point, which is underlining in the red here, is the fact that the fundry protects their technological information, their trade secrets,
07:42
by NDA, non-disclosure agreements, that prevents you to share or publish everything you do with the design rules, with their private information. So it completely prevents
08:02
you to share your work. On the other hand, once fabricated, you have no restriction about the finished product, which is the ASIC. So those two points are the key points that we want to solve. Let's have a closer look at the ASIC design flow. On the left hand side of this slide,
08:27
I put a drawing of a small, very small design, so we can see the individual components. As I said, the design is just a drawing, but a drawing that has to respect a very complex set
08:47
of design rules. That is, drawing rules for modern technologies. This set of rules contains above a thousand rules. So how does that work? First, we have the RTL description
09:09
of a design, which is basically a finite set machine expressed in terms of registers and Boolean equations, complex Boolean equations. We use the logical synthesis to break it down
09:27
in terms of little logical cells, which gives us a netlist. The point of the logical cells, called the standard cell library, is that those
09:41
little cells have a layout counterpart that you can translate this small logical Boolean equation, which is a noun, into a design, an electrical design, that will do the same function. When you have broken down your design, you have to reassemble it into a single
10:06
layout, which is done basically in two steps. The placement steps, which just place all those little pieces of layout inside an area, and then the routing step, which draws the wires
10:21
that connect them, the electrical wires. And then you get your complete layout expressed in terms of GDS or AP file. This is basically a vcycle into which the library, which is underlined in a light background, is the pivotal points. So you break down into the
10:50
library, and then you assemble them. As I just said, the standard cell library is a key point of the design flow. The one we use has a long history. It starts with the
11:07
Essex Lib1, which has then been adapted by Naoshiko Shimizu from Tokai University to better fit the deep submicron rules. It contains 89 cells, logic gates, deflyprops,
11:21
multiplexer, and so on. It is well validated because we have built some design with it and checked that they work. But in the end, what we use now is another kind of portage, started based on the topological structure of an Essex Lib, or Essex Lib, that has been made by
11:46
Stav Veraghen from Chips Formaker with its FlexLib library and the PD-Chemister. So it's an attempt to be portable across technology but still getting close to the
12:02
technology rules. This is what we use throughout all the Coriolis projects now. Here is a little bit more detailed view of the design flow, of the ISAIC design flow.
12:20
So we want to emphasize in this slide the part that we are working on, which are the physical synthesis and the cell library with in cooperation with PD-Chemister on Chips Formaker. And the other part we aggregate. So the design flow starts with RTL
12:41
generator, which can be anything that generates Verilog or VHDL. You have EMIGEN, Chryzels, Pinellar HDL, System C, System Verilog, and maybe some others that I forgot. And this is a complex choice because there are a lot of advantages to any of them,
13:06
and disadvantages. So it's a trade-off. I won't go into the discussion about those kind of trade-offs because it's almost a short discussion. So we see that we can validate with VHDL. We have the logical synthesis,
13:22
validation again with simulation, and we have to validate the layout with the TRC. We will go into that in more detail in the following slide. So the right part, which is in a light red background, is the part which is not publishable.
13:48
That is, which is covered by the NDA. But fortunately, last year Google released its SkyWater Free PDK Open Design Kit. So fortunately for that design kit,
14:05
all this part can be published. Now let's have a look to the logical synthesis part. As almost everyone out there, we are relying on IOSIS to perform the logical
14:20
synthesis. But as we are aggregating tools, it is a nightmare of file translation. For example, here we start from VHDL, then we have to translate it into Verilog. Then IOSIS can use it, generate a BLEF file as output, and we have then to translate
14:46
the BLEF file into the Coriolis special subset of VHDL, which is called VST for VHDL structural. Hopefully this will improve in the future years and be more integrated and
15:03
simplified. At the other end of the design flow, we found the validation. I mean that when you have placed and wrote your design, you will need to check that the layout that you
15:22
have got is as error-free as possible. It is not always sure that it will be, but at least you must perform all the verification possible. So there are three kinds of verification. Starting from the GDS file, which is your layout, you first perform a DRC or design rule
15:47
checking. That means checking that all that you're drawing is completely correct, respects all the rules dictated by the technological node. For example, that means that there is no
16:03
wire too small or too close to each other. So that's basic verification. Then you need another tool which is an extractor, which is currently and very recently we used OpenRCX, which performs an extraction of the netlist and you compare the extracted netlist with the
16:26
reference one with an LVS tool, layout versus schematic, which means that the router has done its job correctly and the wires are exactly connecting the gates like they should. There is
16:42
no open circuit or disconnection and there is no short circuit, that is two wires crossing each other. So that's the second verification, which is very important. And the last one is the static timing analysis. It's based on the extracted netlist but with a more fine
17:07
grained detail level, which is the transistor level. We use the gates inside the transistor and we combine them with the wire from the netlist and we check that all the timings are good, that you are really making all the timing constraint, meaning that the
17:28
propagation time along the wire are all correct. And this is very important if you want to match the working frequency of your design and also check some other
17:41
difficult problem. For that we use the ITAS tool, which is also a tool developed at the Lib6 lab, which is old but very reliable. Now let's have a look at the algorithm.
18:01
At first glance, the algorithms are sequentially organized. First you have the standard cell library, then the placer based on a simple algorithm, then the global routing step, which uses a Dijkstra algorithm, very classic, and finally the data lead router, which makes
18:20
use of an unpublished academic algorithm based on segment rip-up and reroute. But each one of these steps, of course, is NP-complete, but they are not as sequential as they are. For example, one classical problem is the routing congestion. That is, the placer
18:47
clams the cells into too small an area, so the data lead router cannot draw all the data without making overlap. So it must inform, in some way, that that area is
19:03
overloaded and the placer must insert more space for the router to complete. Basically, there are a lot of constraints like that. This is what we really have in terms of interaction, and this has consequences in terms of data structure
19:25
upon which we construct our tools. So the key feature of Coriolis is the hurricane database through which all the tools communicate. And in terms of data structure,
19:43
they make decorations, like illustrated here. The JSON is the hurricane database, and you have the data lead router or the global router, which makes decorations over it and communicates through them. Finally, all those considerations explain the shape of the DoDesign script.py,
20:12
which manages how your design will be placed and wrote. As we have a Python interface, this script is really a mix between Python part and C++ part. C++ parts are used for
20:28
computational intensive work or tasks like placement or detailed routing. But other parts, like the clock tree generation here and some others, are only made in Python. In fact,
20:47
there is not a real Coriolis binary. It's only made of Python scripts and library interfaces in Python. We also delegate as much as possible the task of managing the
21:03
system to Python, because it is already done, and we don't want to reinvent the wheel by doing it inside Coriolis. We have also been busy making new chips. For example, the biggest one,
21:21
the Librosoc, which is 120 kilogates, accounts for 1.3 million transistors for an area of 28 square millimeters. It has been done in the TSMC 180 nanometers technology, and we hope to get it
21:41
back packaged in a few weeks. Staff, there again, did also use our tools to make his own microcontroller chip, which contains a Motorola 68000 and a MOS 6502, including 4 kilobytes
22:04
of onboard RAM. The onboard RAM can be seen at the bottom right corner of the design, that are those four blocks area, because it deduced directly the RAM supplied by TSMC, for which we cannot display the design, the layout.
22:25
So, as I said, it's done in TSMC 350 nanometers, and amount for 26 kilogates.
22:41
The last chip was done by ChipFlow, and it contains a Minerva RISC-V implementation by Londassoc. It was submitted to the MPW4 Google program, which makes use of the Skywater 180 nanometers. It makes use of the Caravelle harness, which is a way to encapsulate
23:07
your design for measurements, and it accounts for about 57 kilogates. What are we going to do for next year? The first item is to improve the speed of the
23:28
placer. The placer gives high quality placement, but unfortunately, it seems more sensitive to the area of the placement than to the number of tender cells, which is quite
23:43
strange. We will work on that. Then, we will also work on density-driven placement, that is, start to introduce the loop, the retraction loop between the feedback loop, sorry, between the placement and the global routing. And at the same time, we will also interest ourselves
24:06
to the timing-driven placement, because they require similar functionalities or features. And in that same movement, we will also rewrite the netlist extractor and comparator, which are
24:24
already present inside Coriolis. But unfortunately, their implementation is butchered, so we will rewrite them from scratch. And finally, we plan to release a new chip, which is a follow-up of the Librosoc project, and which will be a small gigabit ethernet router,
24:48
and will be a much bigger design. And finally, let's have a little demonstration of what Coriolis can do for you. This example is not completely part of Alliance Check Toolkit yet,
25:11
but it will be in the future. So, first you see that we have some Verilog file, which describes our little design. In our case, it's the 6502, the most 6502. So, we have
25:29
the RTL representation of our design. We also have the little DoDesign script, which will tell Coriolis what to do, how to place and route your design.
25:48
There is some instruction inside, but not too much to customize by yourself. Most of them can be copied from one reference script to another. So, it's very simple.
26:01
And finally, a little Mac file, which is, here again, mostly generic, into which you have just to indicate what is your top Mac file. So, as I said, it is mostly done by Mac file. So, the first step is to generate the, is to call IOSIS and perform the logical synthesis.
26:26
So, we do that by make VST. So, people familiar with IOSIS did recognize its output. Now, it has been processed by IOSIS,
26:40
and then the output BLEF file has been translated into a VST file, VHDL structural, which is loadable by Coriolis. If you look at VST, you see that we have the relevant file. So, now we can run truly the place and route step, this makes TGT, and run the script.
27:11
We run the design. Here we go. So, I activated the step-by-step. It is a debug feature,
27:22
but it is useful for demo also. So, what you see here is the core, and around it is the RS, because it is the demonstration using the Caravelle RS for the Google Skywater program. So, we have added the design. Now, we have built the clock tree. I will make a zoom on the
27:46
center area, which is where the chip processor is located. So, you see the clock tree, unconnected yet, but built prior to the placement. Then, we perform the placement.
28:03
This is the simple algorithm that works, and we display the lower bound placement, that is the one with the shorter distances. And as you can see, the lower bound and the upper bound converge slowly together, which explains the progressive spreading of the cells
28:22
over the area. Now, we have performed the placement. So, I will start to display one net for a nicer demonstration. I did choose this one, the C7. So, what you see now is the
29:10
fly line representing the net. I will perform a zoom around the net, so we see it better as it progressively refines. We are before the global routine, so we only see a fly line
29:24
connecting all the terminals. Now, we will see the global routine appear. Here, we have the global routine, and the trunk of the net. Here, we see the global routine. We zoom.
29:57
Then, after the global routine comes the detailed routine. Here we go. And finally,
30:04
you see it has just submitted a small adjustment, and the global routine is finished. The detailed routine, sorry, is finished. And you can see that any overlap has been solved.
30:24
Now, the whole design has been finished, and you see that it's connected to the harness. We change the power distribution of the Google Skywater harness by only putting vertical lines. Here, big vertical lines that make them big wires to the elementation. If we zoom again,
30:50
we can see them. So, now you have a completed design, which can be sent to the Skywater foundry through the Google program. Thank you for your attention. So, thank you very much,
31:32
Jean-Paul. We have any questions, please do type them in the main conference room.
32:03
It's nice to see that we've had some questions and interaction. Thank you, Jean-Paul, for interacting with people whilst your talk was actually live. We have the one
32:29
from Adam. Does a specific PDK imply a specific foundry? Are more open PDKs upcoming by any chance?
32:41
Are more open PDKs coming by any chance? This is a delicate issue. The foundries are a bit jumpy. Skywater, I believe, through the Google sponsored program are considering a 90 nanometer.
33:05
There's a huge number of hoops to jump through before that happens.
33:46
What else? We've got seeing NWK asks about Serano PyCell Studio.
34:02
This is your parameterized approach. Oh, hello, Jean-Paul. The thing is your parameterized approach is sort of a template or a wizard that generates the layout. That's Staffs FlexLib. Yes, it can do that. You combine the PDK rules with the Python-based parameterized layout of
34:30
the cell, which is sort of a virtual layout, and then it generates the actual layout that's compliant with the PDK. Whereas NSXLib was done before, that is independent of it,
34:49
and that's a different approach. So, you can either use NSXLib or you can use FlexLib. You can see Adam, you're typing. By the way, this will transfer over to the
35:33
chorus room. I will drop the chat. Yes, of course, Jean-Paul. No, we weren't able to
35:44
hear you. Your microphone is still listed on mute. I'm just waiting for Adam and Nathan to
36:16
type. And Jean-Paul, bless him, we're waiting for, see if he can resolve
36:26
microphone. So, Nathan's questions, do you extract timing information from the generator
36:49
standard style through spy simulation to create Liberty files? And then it is the place and timing driven. We're still waiting for Jean-Paul. See if he can sort out the microphone.
37:08
Let me see if I can remember the information. If I get this wrong, Jean-Paul, you can correct me with the chat. Do you extract the timing information from generator standard styles?
37:22
Yes, as part of the Librisoft 180 nanometer design, Jean-Paul added spice netlist extraction, and to do on that is to add
37:48
capacitance etc in the parasitics, but it's got the basic information. And then on that, that will then you can put into logical equivalence checking as well as spy simulation.
38:10
And is this right, Marie Minervé did put it into high task YAGL to do a transistor
38:22
and mixed transistor gate level static time analysis? Is the place and route timing driven? Yes, I believe so. That's a key feature of it. Adam is asking who,
38:59
Jean-Paul is going to disconnect and reconnect to the Q&A cleaning to see if he can solve the
39:04
microphone issue. Who in practice will be using the tools, research institutions, small companies or individuals? All three. One of the key things is at the moment is the NDAs
39:23
in the sort of basically equivalent to a worldwide cartel basically prevent research institutions and security researchers from doing, you know, academics from being able to publish any of their results. So this is one way to break that. Small companies would,
39:51
yes, 180 nanometer, I don't know if you're aware, is extremely cheap and is the largest and most commonly used geometry in the world. Last time I checked, it's only in production,
40:08
you're only looking at 600 US dollars for an eight inch wafer. And so the whole idea is that yes, you will be able to use Coriolis 2 to your full GDS 2 files rather than having to
40:27
spend a quarter of a million dollars a week on licensing of proprietary tools. That's a mad cost which makes it completely impractical to consider doing an ASIC.
40:44
You know, the volume said you have to sell, that it will be enormous to cover your costs, whereas if you've got labour open place and route, many more people can consider it. And yes, I'm an individual and I've been doing layout
41:04
and working with John Paul on this. Re-connected.
41:37
Nathan, I can't see your typing, so we'll just wait for you.
41:56
Nathan, who's your sponsor for your quarterly chip fabs, they're paying cost for a procedure fabs on the QI-WATER version of the process.
42:01
Yes, they are. So there is now chips for makers has done a Skywarden 130 nanometre flex lib port. Let me just find the repository. So previously in the chat, I linked the
42:34
3PDK45 version cell library, so you can do your layout with that.
42:43
Because 3PDK45 is an academic PDK, it's not intended for actual sending to, you know, GDS 2 files sending to a foundry because there's no fab that actually exists which would take it.
43:02
But this chips for makers PDK Sky 130 nanometre is intended to work with the Skywarden 130 nanometre process. Thank you, John Paul. We do not have time in place and route yet,
43:24
should be working on features this year. That's the thing sponsored by NLS, isn't it?
44:02
And so there is at least one project that has submitted to eFabless using Coriolis 2 with chips for makers Sky 130 PDK.
44:37
Hi David, nice to see you here. Thank you, Nathan. I'm sure John Paul really
44:58
appreciates that. It's been a lot of work. It's been, John Paul, this has been,
45:08
project has been running since 1993, 94. And one other thing, there is a Japanese
45:22
foundry in something very, very large. Free software projects come submit to its, I forget the name of the university, but they're working with a company that
45:41
uses, for training purposes, I mean, Pentium 3 was a 180, yes, exactly. 400 megahertz DDR3
46:03
memory was done in 130 nanometre. So, sorry, 800 megahertz DDR, so a 400 megahertz clock rate. If you look, you can see DRAM chips were in 130 nanometre. That's, you know, it's perfectly possible. Yes, Alliance started in the 90s here,
46:43
and have been slowly converting from that C and C++ code over to Python, but keeping the high-performance parts in C++. If anybody actually wants to try it out for themselves,
47:06
I'm just going, whilst questioning is still running, I'm going to drop a link to the Coriolis install script, which we've been running within the LibreSoft project.
47:21
There you go. If you want to actually just run an automated auto install, there you go. There's a script to do that, which I've dropped into the chat. Let's say git.libresoft.org, and it's on the dev end setup repository.
47:49
So if anybody would like to continue talking with Jean-Paul, I will drop the link in the chat, and thank you very much, Jean-Paul, for such a fascinating
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talk. It's really appreciated. I think really, really important work that you're doing.