QtRVSim—Education from Assembly to Pipeline, Cache Performance, and C Level Programming
This is a modal window.
The media could not be loaded, either because the server or network failed or because the format is not supported.
Formal Metadata
| Title |
| |
| Title of Series | ||
| Number of Parts | 542 | |
| Author | ||
| License | CC Attribution 2.0 Belgium: You are free to use, adapt and copy, distribute and transmit the work or content in adapted or unchanged form for any legal purpose as long as the work is attributed to the author in the manner specified by the author or licensor. | |
| Identifiers | 10.5446/61771 (DOI) | |
| Publisher | ||
| Release Date | ||
| Language |
Content Metadata
| Subject Area | ||
| Genre | ||
| Abstract |
|
FOSDEM 2023507 / 542
2
5
10
14
15
16
22
24
27
29
31
36
43
48
56
63
74
78
83
87
89
95
96
99
104
106
107
117
119
121
122
125
126
128
130
132
134
135
136
141
143
146
148
152
155
157
159
161
165
166
168
170
173
176
180
181
185
191
194
196
197
198
199
206
207
209
210
211
212
216
219
220
227
228
229
231
232
233
236
250
252
256
258
260
263
264
267
271
273
275
276
278
282
286
292
293
298
299
300
302
312
316
321
322
324
339
341
342
343
344
351
352
354
355
356
357
359
369
370
372
373
376
378
379
380
382
383
387
390
394
395
401
405
406
410
411
413
415
416
421
426
430
437
438
440
441
443
444
445
446
448
449
450
451
458
464
468
472
475
476
479
481
493
494
498
499
502
509
513
516
517
520
522
524
525
531
534
535
537
538
541
00:00
Computer programmingUniverse (mathematics)Computer architectureGoodness of fitComputer animation
00:29
Computer programmingNeuroinformatikStudent's t-testSoftware1 (number)Computer engineeringSoftware engineeringComputer hardwareReal-time operating systemComputer architectureComputer simulationComputer animation
02:24
Cache (computing)Computer programmingComputerComputer architectureReduced instruction set computingElement (mathematics)Faculty (division)Spring (hydrology)MathematicsPhysicsComputer simulationUniverse (mathematics)Materialization (paranormal)Revision controlPerspective (visual)BitVideo gameWave packetComputer architectureComputer architectureFaculty (division)InformationGroup actionWindowFreewarePresentation of a groupForcing (mathematics)Projective planeWeb browserSlide ruleComputer animation
04:51
Computer programmingCache (computing)Computer programVirtual machineComputer fileCore dumpRead-only memoryStructural loadExecution unitHazard (2005 film)Address spaceMachine codeLoop (music)Wireless Markup LanguageWordBranch (computer science)Computer simulationStudent's t-testMikroarchitekturNeuroinformatikSingle-precision floating-point formatCycle (graph theory)Structural loadMachine codePhysical constantOperator (mathematics)Computer programmingArithmetic logic unitLoop (music)ResultantWhiteboardData storage deviceVisualization (computer graphics)Semiconductor memoryGame controllerView (database)Mechanism designBranch (computer science)outputDeterminantComputer fileMoment (mathematics)Digital electronicsAddress spaceBus (computing)Direction (geometry)Equaliser (mathematics)LogicWordRight angleCache (computing)Execution unitGraph coloringSpeech synthesisMereologyGraph (mathematics)DebuggerComputer animation
10:38
Cache (computing)Computer programmingBefehlsprozessorSemiconductor memoryComputer configurationComputer virusGraph (mathematics)Student's t-testComputer animation
11:20
Computer fileVirtual machineCache (computing)Computer programmingLoop (music)Computer configurationAssembly languageComputer fileProjective planeComputer programmingSelectivity (electronic)Semiconductor memoryException handlingText editorClosed setQuicksortWeb 2.0Multiplication signComputer configurationVolumenvisualisierungComputer animation
12:20
Computer fileVirtual machineRead-only memoryComputer programmingCache (computing)WordQuicksortMeta elementBit rateHill differential equationComputer programAddress spaceDegree (graph theory)Associative propertyBlock (periodic table)Graph (mathematics)NumberCore dumpWritingFocus (optics)QuicksortMultiplication signShape (magazine)Cellular automatonWindowStudent's t-testMachine codeSemiconductor memoryComputer clusterCache (computing)Computer simulationSelectivity (electronic)Particle systemStructural loadConfiguration spaceNumberStatisticsBlock (periodic table)Graph (mathematics)MereologyDegree (graph theory)Computer programmingData structureDecision theoryDifferent (Kate Ryan album)Right angleoutputView (database)Set (mathematics)Computer configurationComputer animation
16:07
Cache (computing)Computer fileVirtual machineComputer programmingCore dumpComputer programSoftware bugCAN busExecution unitHazard (2005 film)Structural loadMultiplication signMereologySemiconductor memoryBefehlsprozessorView (database)Level (video gaming)Game controllerComputer fileExecution unitComputer configurationHazard (2005 film)Branch (computer science)WindowCycle (graph theory)LogicComputer simulationUniqueness quantificationComputer hardwareStudent's t-testMaxima and minimaComputer-generated imageryCache (computing)Computer programmingGraph coloringResultantSelectivity (electronic)QuicksortAbstractionTDMADifferent (Kate Ryan album)Task (computing)Connectivity (graph theory)CompilerInsertion lossCore dumpCASE <Informatik>Set (mathematics)Computer animationEngineering drawing
22:17
Software testingCache (computing)Computer programmingComputer programAssembly languageCore dumpRead-only memoryConfiguration spaceLevel (video gaming)Function (mathematics)Hazard (2005 film)Execution unitSemiconductor memoryMathematicsMereologyResultantComputer fileConfiguration spaceLevel (video gaming)Computer animation
22:56
Computer programmingCore dumpRead-only memoryAssembly languageConfiguration spaceLevel (video gaming)Cache (computing)Maxima and minimaGEDCOMExecution unitQuicksortStudent's t-testComputer configurationSemiconductor memoryPeripheralEmulatorVirtual memoryOperating systemComputer animation
23:31
Address spaceoutputWordCore dumpParameter (computer programming)Computer programMaxima and minimaComputer programmingComputer virusAsynchronous Transfer ModeOvalFlagStrutBinary fileComputer fileVirtual machineDecimalPeripheralTemplate (C++)Control flowGreen's functionTemplate (C++)System callOperating systemFreewarePhysical systemGame controllerPeripheralRadical (chemistry)Perspective (visual)Student's t-testComputer fileSemiconductor memoryComputer animation
25:18
Software bugCache (computing)Computer programmingExecution unitHazard (2005 film)DecimalWordGreen's functionControl flowCore dumpRead-only memoryComputer programoutputComputer fileVirtual machineTemplate (C++)Network topologyMomentumAddress spaceComputer simulationAssembly languageMemory managementTask (computing)MereologyStudent's t-testMachine codeWhiteboardSuite (music)Computer fileStructural loadLipschitz-StetigkeitLink (knot theory)Real numberVirtual machineComputer programmingRadical (chemistry)ImplementationSoftware testingPeripheralCompilerRight angleComputer animation
27:08
FAQComputer programmingCycle (graph theory)Computer architectureSocial classSimulationReduced instruction set computingComputerSoftware testingExtension (kinesiology)Read-only memoryStudent's t-testInterrupt <Informatik>Visualization (computer graphics)View (database)Virtual realityGraph (mathematics)HypothesisSoftware developerDistribution (mathematics)Online helpRepository (publishing)Revision controlSource codeSoftwarePhysical systemOpen sourceData storage deviceUtility softwareException handlingComputer-generated imagerySoftware testingComputer configurationSemiconductor memoryVisualization (computer graphics)Student's t-testProjective planeHypothesisConnectivity (graph theory)Distribution (mathematics)Block (periodic table)Maxima and minimaMultiplication signInsertion lossComputer simulationGame controllerCycle (graph theory)Revision controlComputer programmingView (database)PlanningGraph (mathematics)Source codeKey (cryptography)BuildingMereologySquare numberMathematicsSpacetimeMultiplicationBitSlide ruleSoftware developerComputer animation
31:21
Revision controlSource codeSoftwareReduced instruction set computingSimulationComputerSocial classVisualization (computer graphics)BefehlsprozessorCache (computing)EmulatorHypothesisMaxima and minimaComputer architectureData managementSpeichermodellArchitectureHaar measureFaculty (division)Assembly languageHypothesisWordMaterialization (paranormal)Computer animation
31:48
Cache (computing)VacuumEmulationInformationConnected spaceVisualization (computer graphics)PeripheralOpen sourceComputer simulationProjective planeLink (knot theory)Metropolitan area networkPhysical systemNetwork socketCartesian coordinate systemSimulationKernel (computing)Staff (military)Game controllerDevice driverSimilarity (geometry)Field programmable gate arrayStudent's t-testCoprocessorComputer animation
34:21
Visualization (computer graphics)Revision controlGraphics softwareComputer fileCore dumpComputer animation
35:12
Program flowchart
Transcript: English(auto-generated)
00:06
So good morning ladies and gentlemen, I'm Pawel Pisa from Czech Technical University I teach computer architectures for something like 20 years from year 2000 we follow the
00:20
famous professor Hennessy Patterson book about the computer architectures and We have used the original Mipsit simulator which is which has been distributed with the book, but it has got dated so we decided that we need to do something for our students to have a better experience and
00:42
We started first with some simulator and then we switch to RISC-V and this was work Has this work of the Jakub Lupak our student So I hope that everything is working and I pass him a mic and the stuff Okay
01:03
Okay, so good morning
01:21
Over the past decades computer engineers have been creating faster and faster computers meanwhile many software engineers kept writing slower and slower software and In many areas, this is fine but in other ones we need to process pretty much insane amount of data often in real time and
01:44
to do that, we need really efficient software that can exploit the capabilities of the hardware and Only software engineers who understand the principles of the hardware can do that. So to ensure we will have such software engineers we need to teach our undergraduate students at least the basics of computer architectures and
02:07
Because no one nobody wants to learn with pen and pencil anymore we started using graphical simulator so Yes
02:30
So we started with a Mipson simulator as was mentioned which was shipped with the Hennessy Patterson books However, it had very limited features and it only worked on Windows. So in
02:40
2019 Carl Kochi was sitting over there created QTMIPS graphical simulator of the Mips maker architecture And it was continued with a lot of work of dr Pisha here and in 2032 myself with my colleague Max Holman and again a lot of work from dr
03:02
Pisha We have switched the simulator to risk 5 so that we could switch all the undergraduate computer architecture teaching to risk 5 So we are there the simulator is license under GPL free and it's native simulator We are running under QT 5 and 6 it's developed and available on github and
03:25
To better Collaborate on the materials we have joined forces with our sister faculty we are from the faculty of electrical engineering and They are the faculty of information technology and we have created what we call computer architectures education
03:40
Projects and you can find all the materials that we have recorded lectures slides You can find it there and Furthermore to collaborate with as many people as possible. The university has joined the risk five risk five foundation lately so The simulator is called QTR resume and it is currently used by our University the universe technical University in Graz
04:07
University of Colorado at Colorado Springs University of Porto The previous MIPS version is still used by the Charles University in Prague and National Capital history and University of Athens and
04:20
This talk will focus on the teaching and user perspective if you are interesting about how it works inside At least a little bit of it. You can look up the talk that we gave at the risk life international academia and training special interest group So before I dive in as
04:42
Dr. Pisha mentioned you can just open this link and follow the presentation with the simulator running in your browser Great So let's dive in When we get students who have never heard anything about computers before we need to start really simple
05:01
So what we do is that we start with a very simple single cycle Microarchitecture and we show them how basic instructions are processed there. So this is the simulator This is how it looks when you open it. So we will hit No pipeline and no cache to get started and hit start empty because we will use one of the examples provided
05:26
so file examples and simple old and store board As you can see the program is really simple It just loads from one part of memory stores into another and then goes into a loop using branch instruction
05:41
so This is the basic view that we start with and on the right side. You can see detail of the program memory with address of each instruction hexadecimal code of the instruction and the disassembled instruction itself Where the last two columns can be edited directly in this view by double-clicking and writing the instruction or
06:04
pasting the code and furthermore the left more column is A place where you can set breakpoints so you can use it like a GDB debugger or at least the simplest part of that And now we can move to the heart of the simulator and it is the visualization of the pipeline
06:26
So if you look closer on the left We start with the program counter program memory and circuits to update the program counter We load the instruction and here you can see the hexadecimal value of the instruction
06:41
Shown on the bus and it gets to the control unit where we send all the control signals that we need So we are showing the load board instruction. So We need to send send the data from memory to registers we need we need to read the memory and
07:01
We will need immediate value for the arithmetical and logical unit Right here. We can see mechanisms for resolving branches, but this is load board instructions interesting there and Here is our arithmetical and logical unit, which has two possible inputs
07:21
either from registers or from PC or from PC and the other one has either value from registers or from immediate the code here we get the Requested operation of the alu and here we get the signal whether the result was zero for branching and finally here
07:43
We have the data memory if it address and data to be written So We start executing and we see that the instruction load board was highlighted and in the register view that appeared up there We see that value One through eight was written into the register Bank, which is highlighted by the red color
08:06
If we continue we move to the starboard instruction and now the value needed to be red. So it's blue now and If we go back to detail of the view
08:20
We see that we read that value from register and we are sending it by this wire To the data memory to be stored We also read the address from the immediate a code and we are sending death to the arithmetical and logical unit to be added To a register which is in fact zero. So we are just sending the value to the memory and now the memory can write
08:44
So, let's see what happened in the memory Here we can see the address four or four with a value written so it corresponds to the others we have here and to value we have here and Right above it. We can see the place where we read the value from so speaking of the memory view
09:04
Right now we are working with boards, but we can work with other sizes So you can switch the view for the unit to be either word half word or byte Which will work with respect to both little and big Indiana's and
09:21
Once we add cache which will be in a moment we can switch the memory view between direct view of the memory and View when where we are looking through the cache, so we will see also the cache data Now we move to last instruction of very long program that is the branch equal instruction and
09:41
We will see that we take Destination from immediate it's negative. So we're jumping back We add it to the program counter and here we send it back to the program counter You know in the control unit now the signal for branching for the most generic one is active and we see
10:02
That your branch resolving mechanism Determine that the branch should be taken. So we go to the program counter and instead of taking the program counter plus four We are now instructed to switch this multiplexer and take the value computed by the arithmetical and logical unit
10:23
so here we have detail of the program counter and the register itself in the pipeline and As you can see we continue to the load bar instruction so that we can keep You're running in a loop in this example so
10:40
this is a very basic example just for this presentation, but it gives you an idea how we start with the simple assessor and When students have idea what the virus are doing and what it all means we can start speaking about how to make it a CPU faster and Well what we find out that the memory is slow, so we want to cache it
11:03
However, that's not that simple there are many ways to cache it we can cache data we can cache instructions we can Choose different sizes of the caches, and if you do it wrong it will be worse than doing nothing so We really need to think about it. So we switch to the second option in the configuration and add and start empty
11:25
but this time We will hit the button up there, which will open integrated editor With syntax highlight and integrated assembler the other options are to open file to save file close file This is the important one. This is to render assembler and
11:42
Upload it to memory, and if you have some more complex Project you can even invoke external make file Except for back at web assembly where there is no make so We insert a simple selection sort suited you will use for example
12:01
I put it in free column so that we can see the program But it's just a simple selection sort was important here that we have data that will be put into the elf file and later Start into memory, and that will be the data that we want to sort So we save the file so that we don't lose it and we move to the memory view right here
12:24
You can see the data that we have input it and on the right side New windows opens, and it's the detail of the data cache. It has two parts Statistics of the cache performance, and it has very detailed view of the internal structure of the cache and
12:43
The data that are there right now So if we start running the cache was empty so of course we need to edit and we will miss and We will continue adding the value and right now the cache is full So first decision that the students need to understand is
13:03
What shall be a week? so There is a right now. There is random choice, so it affects the First one and we continue running and right now the selection sort will start placing values where they should be So it moves the value number one
13:21
To the first one and you see the yellow Highlight shows us that the value is now written in the cache and the cache is dirty So right now the cache is using bright back policy just to show you the highlight and we can continue and now we switch one with five and
13:42
There was a simple example, so the array is now sorted, but we still need to go over it because the CPU doesn't see that needs to check it and Because we use the bright back policy We also need to run fence instruction to make sure that everything is stored back to the memory So you see there is no highlight anymore and the cache is empty
14:03
And this is a time where we should look at the performance data And we will see that we have quite an improvement of course This depends on how fast memory we have and fast cache we have so in a configuration You can set the penalties for hits and misses so that this data will look according to what you need
14:28
So this is the configuration of the data cache you can see that we can select different shape of the cache Which means number of sets block size degree of associativity, and then we have two policies
14:42
replacement policy, which is at a random last recently used or least frequently used and Bright back policy which can be you can see right back right through two options there So here is how the detail of the shape of the cache looks for two different configuration which in fact have the same amount of data there, but they will probably have quite different performance and
15:08
Also, you're right Yeah, you're right one It's way more complicated so the students can examine What this will do to their particle programs and data loads that they will have?
15:23
Well of course we have also program cache, and I have added this very stupid design where we have just one cell and Well in program you never go to the same Others twice so you can see that we always missed and it's actually worse than doing nothing
15:41
Just example of that And I mentioned that the windows can just appear so if we prepare some example code for students We can insert special pragmas to make the windows appear so that the students who have not seen the simulator before Can just start with all the tools they need so we can show any part we can focus at the rest in memory
16:06
and so on so now We have improved the speed of the memory and We look at the CPU again, and we find out that most of the silicon is just lying there doing nothing most of the time So we want to utilize utilize it better, so
16:25
We see that most of the parts are somewhat independent, so we split it into five parts So let's go to third option. We will choose pipeline without cache and You can see that the image got somewhat more complicated however
16:42
If you remember the previous is all the same So students already invested some effort into understanding But the image was supposed to mean so we don't want to move things around We are just adding the minimum amount of things that we need So that we can continue with a more complex stuff so you can see
17:04
Yeah, we display all the instructions in each stage of the pipeline. We are adding the interstage registers and The colors are not random We are also using that to show But which instructions correspond to each stage of the pipeline in the program view so you can see all the stalls
17:26
yeah, and branches nicely as they progress through the pipeline and Of course we needed to add animated windows to each stage of the pipeline for each fire for both control and data that we have and
17:43
Now we find out that this is not all we need to do Because up until now we assume that okay. We process one instruction instruction is done We continue, but right now we start processing instruction But it will take what former cycles because before we get the results so we have something that's called data hazards and
18:05
That means that if you do nothing we will get all the data because the data from the instruction that we depend on It's not already yet so we can have Hazard spinning two cycles in the next instruction and hazard spinning one cycle
18:21
in the instruction after Technically there is also hazard in the instruction that is after that But this is something that we can solve inside the register file without breaking the abstraction of the pipeline so we will ignore the last case and So what can we do about that well we need to detect those problems
18:42
And we need to counteract them in some way So we are adding hazard unit to the CPU and it has two options First option is okay. We will wait for the data But we said we want to build a fast CPU and waiting is well, not fast
19:04
So we also have option to forward the data as we need it So yeah, it's in the core tab and this is the option so This is the CPU with edit forwarding paths So what we have here is we are adding path from the right backstage
19:22
to get it directly into the execute stage and The multiplexers got bigger and we are adding second path to forward the data from the memory stage So Here is the difference there is Some extra wiring this CPU looks were simple
19:41
But it will wait and that's what we want, but it will cost us more to build it because it needs more components So, let's see some actual examples we are again learning the selection sort I Showed you before so we start running this instructions and right now we have our
20:02
PC instruction that is producing its value to register 10 and The hazard unit started screaming it doesn't like it so It tells us it's not very very visible, but the text in the red is forward So This is the hazard that we have here. And what happens is that?
20:24
this multiplexer gets value to use the forwarding wire from the memory stage and Instead of using the actual value for registers. We are taking the value for the red path and We get here for the arithmetical logical unique value hexa 200, which is what we want
20:44
You don't know that yet, but remember that video it will be important later Okay, we don't want to add the extra hardware. So we will stall insert here instead. So This hazard unit is screaming again, but this time it cannot forward so it's screaming to stall
21:05
but You can see that the instructions if they're right next to each other So that was the first case and we need to actually stall two cycles So we'll run next cycle another knob is inserted and again the hazard unit is screaming
21:23
So right now we have any two knobs But what we have now is that the instructions are far apart enough and we can continue So We get value, thank you 200 X again and we are happy well, and then the simulator of course supports
21:44
The most simple option we do nothing and what happens here? We have the hazard and we get value zero because the register is very initial empty What is the purpose of this setting is that we will task the students to play the hazard unit as?
22:06
And play the compiler so they will have to rearrange the instructions and insert As less knobs as they need to make sure that the result will be correct This will typically be some kind of homework. So
22:20
We don't want to control that manually. So we have a command line interface Which can look something like that and will give you output like that So the capabilities that we have here is to assemble file To set a configuration to trace instruction in each stage of the pipeline To raise changes to memory and registers
22:43
Also at the end to dump the memory and registers, which is the most useful part because we want to make sure that The result is the same as it should be for example when the hazard unit is not available and final sorry And finally when we are want to plug in some data, for example when the students are supposed to sort
23:05
They should not know the data So we have special option to load data into the memory and Right now we have CPU that For undergraduate students, it's quite fast So but it's quite simple
23:22
So now instead of making it fast We will make it more complicated and we are adding memory map peripherals and some very simple operating system emulation So if we open the templates again, you can see that there is template for operating system and It really does nothing special. All it does is prepare for calling system call which is equal in RISC-V and
23:46
We will print hello world to file The file is connected To a terminal. So what we actually do is after running the Yeah, now we get the echo detected you can see that there is something correct written that is detected Cisco
24:05
So we will stop fetching new instructions. So it's more clear for the Students and once we get to a memory Ta-da. Here is our hello world in the simulated terminal and You can see that the pipeline is empty because we are looking at this from the perspective of userland
24:25
So the operating system is emulated and We don't see the instructions in the pipeline we just see that the pipeline was flashed before here it was written to us so this is The system calls that we support it's not much but it's enough to show the basics to the students
24:48
and This is all the peripherals that we can play with mainly using the system calls So this is not peripheral but we have control and status registers well some basic support of them Yeah, we have an LCD display
25:02
The terminal I've already shown you and there are some general-purpose IO peripherals to let's free knobs with buttons and This might seem a little random to you. It's not because we also have this variable part that has exactly the same peripherals and
25:24
The simulator is set up in a way that you can take the same code. Well not assembly code because unfortunately the board is armed yeah, but You can take the same C code and run it both on the simulator and on the real world board and you can move
25:43
back and forward So I said C code so we can't use the integrated assembler anymore, and we did not implement C compiler So you can use clang or risk or GCC to compile the file into elf
26:01
Which of course is to be static linked and what we do now is instead of hitting the start empty we will Here insert the elf executable, and we will hit load machine So this is example of some program that Writes to the LCD display, I will not show you the code here because this is one of the tasks that we give our students
26:29
But I can show you This code. This is available on our gitlab right link here and It is test suit
26:41
Simple for malloc from the new lip so you can link your lip Codes to the new lip and use it in our simulator or at least some basic parts, and we have tested that with malloc So you can run this and it's connected to the terminal so we can see that Some dynamic allocation takes place and some checks take place and the tests are running successfully
27:04
so now you can use actual dynamic allocation inside a simulator and now some conclusions, so Frequently asked questions is the simulator cycle accurate. That's very important one. Yes, kinda
27:22
The thing is we always assume that the memory has enough time to finish and if it doesn't See people will wait. We will not like insert stores or anything We just the memory will finish, but that's the only exception otherwise. It's inside written in quite similar style to
27:41
Balloq system So it is compliant with the official RISC-V test and yes, I can please see this Yes in the previous version. We have added that and it's integrating into our CI So every new changes are tested against that We support the graphical part supports the
28:02
RISC-V I with multiplication and also with control and status registers instructions The command line also supports 64 bits However, I yet need to find out how to fit the 65-bit values into the visualization because it's already quite full
28:21
and we don't have a virtual memory yet, but Somewhere here in other room. There is a students who are already promised to take care of that in the next year. So In a year, he might be presenting that change here. So we'll see So what we plan for the future if we are very close to adding interrupt support
28:44
We would like to add compressed instructions and support because that's quite key part of RISC-V the only trouble there is it's pretty hard to I'm not sure how to fit it into the program view because then It needs to be processed sequentially and I'm not sure how to show it that the students see that it's really half
29:06
We're of the size so That's plan. Also the instruction encoding in the RISC-V is Somewhat special is especially around immediate. So I would like a visualization of
29:23
Each components The blocks that the instruction is composed of so that that can be seen for each instruction and inspected and edited Yeah, we want to We want to be able to run a very minimal RISC-V Linux target
29:41
I mentioned the 64-bit visualization and the program In that also the memory in it another nice thing would be to visualize The utilization of the pipeline the image that is typically in every book when you have squares for each Instructions and you see the spaces where no instructions were executed
30:03
So it would be nice to add and also even when I made these slides I would really love to have an option to step back because I went one instruction Too far and it would be really hard to do it with all memory and everything But at least for the visualization of the pipeline, I would really like that
30:23
so If you are a teacher represent educational institution and you want to use the simulator Please do if you have some problems conduct us. We'll be happy to cooperate on that if you're a student or developer This is open source project. We accept full requests and Usually the way it works is that students do their final thesis on this project
30:43
so far free and If you are distribution maintainer, you could help me with making putting in the official packages So You can get the source at GitHub and we also provide more executables for Windows, Linux and Mac and we have
31:03
packages using the OpenSUSE build system for Ubuntu and Launchpad for Ubuntu, Fedora, Fedora and Debian and there are also packages for our and next packages because those are those that I use and
31:20
As we mentioned we we have the online version as well, so If you would like to read more we have some publications the thesis and our paper from the embedded word conference last year so those are available and We have this subject and you can find a
31:42
Lot of the materials at the comparch. It's some of the materials videos Some are in Czech many are in English and That's all from me. So thank you for attention and for so many people coming
32:01
Thanks Tightly coupled is the simulation of the processor and the visualization I was thinking would it be possible to somehow connect something like models in with the VHDN model? Sure, so the question was how tightly coupled is the visualization and the simulation so it's
32:29
Separated project that is linked together and it's only connected with some data passing and QT signals so we already have the Visualization and the command line that are completely separate and they are just connecting to the same signal
32:43
So it's quite well separated, but it's not at all stable Any other question sure
33:02
Okay, if you have no other questions, we do not work only on the simulators, but we do even the design of Peripherals. So for example, we have open source can can every staff We work on open source replacement of matlab of similar and sim link
33:20
Okay, it is toy, but we work on such stuff. So if you have interest we have their links to our other project We have experience with motion control. I have about 30 years of experience of its embedded system design including infusion systems for medical applications I have contributed to our TMS project
33:44
which is used in European Space Agency and so on we do a VHDL design for the Experiments of its space-grade FPGAs and so on so This is the work which we do to help us to our students. It is a lot of work something like eight
34:02
Man years of work in the simulator But it is only for our students, but we do even the stereo stuff for the world For example in socket can in mainline Linux kernels are our oven stuff contribution drivers and so on Okay. Yeah
34:22
So yeah The actual visualization of the pipeline because I remember there's something like this and say out there quarters Well
34:42
It is ours yes the visualization that you see is actually an SVG file that has special annotations which connected to the core previously it was done by a handwritten QT objects, but I was not Like okay to work with that. So I switch that to the SVG version when you can
35:04
Design it all in graphical editor and then you just connect it to the simulator. So that's completely ours