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Hardware-Aided Trusted Computing in High-Level Synthesis (HLS) for FPGAs

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Hardware-Aided Trusted Computing in High-Level Synthesis (HLS) for FPGAs
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637
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N. N.
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CC Attribution 2.0 Belgium:
You are free to use, adapt and copy, distribute and transmit the work or content in adapted or unchanged form for any legal purpose as long as the work is attributed to the author in the manner specified by the author or licensor.
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Hardware accelerators are being increasingly integrated into today’s heterogenous computing systems to achieve improved performance. However, the resulting heterogenous hardware also increases the challenge to ensure the security of these accelerators. High-Level Synthesis (HLS) automates the creation of a register transfer level (RTL) description of a digital circuit starting from its high-level specification (e.g., C/C++/SystemC). In this talk, I would like to discuss different extensions and methodologies to High-Level Synthesis (HLS) compilers for generating secure accelerators. Precisely addressing the HLS vulnerabilities like side-channel listed in Common Weakness Enumeration (CWE) list.