Coriolis is a suite of software for taking chip designs and turning them into ASICs (aka VLSI design). It is silicon-proven, having been used with Alliance auto-scaleable nsxlib Cell Libraries to produce ("tape out") NDA-free GDS-II files that resulted in successful working 180nm ASICs, and has been used in ASICs up to 800k gates. The input is HDL (verilog, VHDL, and yosys RTLIL) and the output is 100% complete GDS-II, with IO pads, cells, SRAMs all fully "Placed and Routed", ready for ASIC manufacture. However unlike traditional P&R software (which may or may not have had, at some point in its development, a scripting language added as an afterthought), coriolis2 is written in a hybrid of c++ and python modules. Layout is done not by a file format that must be loaded by a GUI: layout for each ASIC is actually a python program that, through the coriolis2 python modules imported by that program, reads the HDL, reads the Cell Libraries, and, fully under parametric programmatic control, creates the layout. This talk provides a demo walkthrough of coriolis2 in action, to produce an actual GDS-II layout including the IO Ring and IO Pads.