Alliance / Coriolis2
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00:00
Parametrische ErregungOpen sourceProcess modelingComputer animation
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25:05
Element (mathematics)Computer animation
Transcript: English(auto-generated)
00:41
Hello, everybody, and welcome to this short presentation to the Coriolis toolchain. Coriolis is a toolchain to perform the last step of ASIC design. That is, create a layout to be sent to the fundry.
01:02
A layout is just a big, complex drawing, and the fundry is the factory which is tasked to translate this big drawing into a functioning sheet. So Coriolis was developed to allow academic to check
01:26
and test their own algorithm without being hindered by the commercial tools with closed sources. So they can really access the data structure, the database,
01:42
and make any adjustment they see fit. It is also developed to allow individual and small or medium businesses to access the ASIC market. So that being said, let's have a look at what we can do.
02:03
So the first I will take as an example 6502, which is a small chip which was historically the chip of the Apple II computers, just because it is small and allow the tools to run fast in this presentation.
02:21
But of course, the tools can manage much, much bigger designs. So the first step is to take a description of your design on your chip in a high-level language, some kind of a functional description, and to translate it into small in terms of logic gates,
02:48
more or less like an FPGA. So we use the same tool as for the FPGA, the same free tools, which is YoSIS. So this is what we've done here.
03:02
We do here. We'll obtain a netlist, which is just the same design, but broken into small pieces, small logic gates, each one having a layout. So that has been done here.
03:22
We can then start Coriolis with running CGT, which is the Coriolis graphical tool. OK, here it is. So we are going to start the Python script,
03:41
which will build the whole chip. Coriolis is built upon C++ for the algorithmic and computational intensive part, and Python for all the glue and all the rest.
04:02
The script is called glue design, but it can be called whatever you like. Here it is. So at first, we define the areas into which we
04:22
will make our ASIC. The outer square is the boundary of the whole chip, and the inner square is where we will put the logical function. Usually, they should be close together, but as our chip is very small compared to the IOPN
04:44
it will need, we have a lot of space in between. But this is not the normal case. We have also the five dots here, which in fact define the clock tree. We will see that in a few seconds.
05:01
So here, we have drawn the trunk of the clock tree to ensure that all the flip-flops get the clock signal almost at the same time. We need to build a special structure for the clock. And this is called the clock tree.
05:20
At least we use that technique in our tools. We use a clock tree, which is shaped like an H. This is what you see here. The clock starts here and gets distributed by there on the leaves. As the design is small, there is one level of clock tree,
05:41
but if it were bigger, you would have seen multiple levels of H3. So the next step is to perform the placement. That is, you have a design which has been broken into standard cells, which are
06:01
little bits of logic elements. So now, you need to place all those logic elements in this area without overlap and with a minimization of the total wire length. That is, you don't want to have long wires. For all kinds of reasons, you want the shortest wire
06:23
possible. So here we go. So you can see the algorithm at work. It's an analytical algorithm, which is more or less force-directed placement by analogy
06:40
with a physical system. And all the wires are like tiny springs, and we want to minimize the energy of the whole system. This is a classical algorithm for solving those kinds of problems. And those problems are very complex.
07:03
They are NP-hard and very difficult to solve. So you see, it is almost finished.
07:22
So now you see that all the overlaps have been solved, but they always remain a little bit of free space. You see here or here. And we have to fill them with dedicated cells, which are filler cells.
07:40
Filler cells have multiple functionalities, but I won't dive into that in that short presentation. So here it is. And you see all the free space has been filled. The next step is now to draw the wire.
08:00
The first step was to place the cells, that is the tiny bits of logic. And now we have to connect them together by wires. And that is done. It is the global routine, followed by the detailed routine. So here we are.
08:21
We start the global router. We add the power lines and a lot of wires, which have dedicated routine. But now remains all the ordinary wires. So this color, I don't know its name.
08:41
It's not red, purple. So you all see a great purple area, because there is a lot of fly lines, all overlapping each other. So you only see purple. I will distinguish one wire, one net, to better detail
09:06
the wire building process. So for that, the controller, I will select one wire.
09:36
I show it. So here we have the specific fly line of this net.
09:43
So this can be understood as a request to connect. We need to connect all those points together with the wire. So this is what will be done by the global router.
10:01
Here it is. The global router has built the trunk of the net. You see that there is a little bit of purple that remains at the end of the wire. We did route at coarse grain. That is, we don't have the completely detailed routine.
10:24
You see here, it's running on the axis, on the center of the G cells. And we have to finish the routine. But we have already an idea of what the routine will look like.
10:43
So this was the global step. Now we will enter the detailed routine. The first step is to finish the wires. So here, you see that no purple fly line remains.
11:03
We have a complete wire. And it may seem finished, but it is not. Because what we have here is just wire, but they may and they will overlap with other nets. That is, the last step and the most difficult step
11:22
of the detailed routine is to solve the overlaps between nets to avoid any short circuit. So the router will displace or even break at some point the net to avoid those overlaps. So this is what will be done.
11:41
So you will see a little bit of change. Here it is. It has been done. So it has slightly changed and completely solved the overlap.
12:01
So now, another interesting feature of Coriolis is its ability to be customized. For example, now that we have made the global routine and the detailed routine, we can choose to display the G cells.
12:23
Here it is. I will make a zoom back a little for a better understanding. So you see a wire. I will unselect that wire. So everything is displayed in full color. So this is the density map of the G cells.
12:43
This expresses the density of wire per G cell. And this is its scale, meaning black is cold and without wire and white is hot with a lot of wires.
13:00
You see those wires are linked to the power lines. And this is because we don't want the router to be near the power line for ordinary signals. So what interested us is mostly the center. And you see, for example, that the most dense part
13:21
of the design is here. But this is a drawing layer that we piggyback on Coriolis. And this is very helpful for people who want to design algorithm on perform checks and add some specific information of overlays to debug.
13:42
In that same respect, we have the inspector, which allows us to browse through the live C++ database. For example, here, we look at the corona, which is the cell which is currently loaded in the viewer. And for example, I can go, I see all the properties
14:01
and all the attributes of the C++ object, which is a cell. And then I can go down, for example, look at the net map, which is all the nets, and see all the nets, and then go down for the nets, go down for their component, and so on. And here we have all the components composing this net.
14:22
The net being, I don't know which one it is, core subsecate zero, and so on. So this is very helpful, not for ordinary users, but for people who are working and developing Coriolis to control and debug live the data structure.
14:45
This is very helpful. So disable it, and now we are going to finish. And this is it. We have our complete chip with all the corners, all the pads,
15:03
and it is ready to be sent to the funery. So we can look here for example, for the corners, and see the terminal cells. Those are the soldering pads of the IO-pads.
15:23
But OK. So thank you for following me until now. And I hope you did enjoy this small presentation.
15:44
So that will be all for today. Goodbye everyone.
16:08
More approachable? Is that a fair statement of project goals for the Coriolis 2? Yes.
16:21
We have basically two goals with Coriolis. The first one is to give academics an access to a tool that they can customize and play with, and implement their algorithm as they see fit, without being hindered by the closet code from the vendors,
16:43
if you have classical CAD tools. And the second part, the second aspect, is to allow individual or small businesses companies to have access to the magic market. That's basically our two goals.
17:00
So who is using Coriolis 2 right now? Who is your consumer for this tool? I don't have consumer per se, for now. We are working with Luke for his Librosoc, and also with staff.
17:23
Maybe, I don't know if it has been introduced yet. We work with staff there again to produce a first chip. That is, Coriolis is not finished yet. It will be in maybe two months when we will be able to send our first tape out to the fundry.
17:47
Otherwise, we already have done chips, but not fully with Coriolis. We did them with Alliance, and they were smaller.
18:00
So strictly speaking, nobody is using it to make chips yet. But the problem is that you can use it only when it's finished. It has always been a very big problem with those kinds of tools,
18:26
because you can only use them when they are finished. You cannot send to the fundry a half-finished design. So we are closing the tipping point where the tool has the minimum feature needed
18:42
to be able to send something in the fundry. And at that point, people will start to use it, and can start to use it, really. So that brings up an interesting question. So can you describe the Alliance relationship to Coriolis II?
19:07
Yes, so Alliance was developed, was started to be developed in the 1980s. As a complete VLSI CAD tool.
19:21
So it was covering all the aspects of the toolchain, that is from the high-level description, down to the layout. And Coriolis is only a re-implementation with newer tools and more powerful algorithms,
19:40
but only of the place and route part. That is what is called, usually, the RTL to GDS II part, or sometimes also called chip compiler. So it's only the last part of Alliance,
20:05
and it still can be used in combination with Alliance, but also with newer tools for logical synthesis, like IOSIS, for example, or any other high-level tool. You mentioned that reproducibility is one of your core design goals,
20:28
that these need to be, these tools need to be reproducible, no matter who is running them. And at the same time, you're describing an optimization routine.
20:42
Can you talk a little bit about how you went about ensuring that optimizing on one machine versus optimizing on another is going to get you to the same, you know, hopefully globally valid result in the layout?
21:04
Yes, basically everything is sorted or have an idea. The basic between reproductibility is that every object inside the data structure or the algorithm
21:20
is either identified by its position, for example, or its idea. I mean, we get sorting on the geometrical position or area or whatever. In case of a strict equality between two objects, because they are exactly the same size,
21:41
or they are put exactly at the same position, we use the idea of the object. And the idea of the object are created sequentially from the passing from disk. So if you read the same file from disk, you will get the same ideas.
22:01
And then the algorithm always sort things according to either their geometrical properties or their ideas. So we ensure that everything is done exactly in the same order. It's to get something reproductible. The idea is to get everything ordered always
22:22
in the same order. That makes sense. That makes sense. So your eventual outcome is going to be driven only by the inputs that are stored on disk
22:42
and not any sort of external random generation to introduce some variability into your system. You can keep that to a minimum. Are there limitations on the nodes that Coriolis can route?
23:06
Yes, of course. For now, we target the 180 nanometer. But the idea is that we will add features
23:20
to reach lower nodes. But for now, we can only reach 180 nanometers. Okay, what drives your constraint on that factor? Is it merely a reasonable calculation time or is there additional aspects that are limitations?
23:42
No, it's not computation time. It's the timing closure, mostly. As we go down, you have timing constraints which get more and more complicated to satisfy. And we need to develop specific algorithms
24:00
to take account of those constraints. And we have not done yet. We have started to implement it, but it's still a long way. Right, what is your, can you describe a little bit about what your verification process is?
24:22
And obviously, designing for a hardware tape-out is, you know, once you go to the foundry, that's a...