AV-Portal 3.23.3 (4dfb8a34932102951b25870966c61d06d6b97156)

Hardening the Operating Systems against transient faults

Video in TIB AV-Portal: Hardening the Operating Systems against transient faults

Formal Metadata

Hardening the Operating Systems against transient faults
Dealing with external interrupts
Alternative Title
Operating System hardening : Dealing with external interrupts
Title of Series
CC Attribution 2.0 Belgium:
You are free to use, adapt and copy, distribute and transmit the work or content in adapted or unchanged form for any legal purpose as long as the work is attributed to the author in the manner specified by the author or licensor.
Release Date

Content Metadata

Subject Area
We are modifying the Nova hypervisor to protect the operating system it hosts, against frequent transient faults resulting from cosmic radiations or manufacturing defects in the CPU. The method relies on the CPU internal exceptions management mechanisms, redundancy of execution and the machine check architecture. Here we will present how to deal with external interrupts, that is one of the challenges faced when it comes to execute short sequences of operating system's instructions twice. Ton erst ab Minute 3!
Operations research Interrupt <Informatik> Physical system
Windows Registry Boss Corporation Computer font Game controller Digital electronics Connectivity (graph theory) Virtual machine Combinational logic Virtualization Mereology Cartesian coordinate system Computer programming Performance appraisal Crash (computing) Befehlsprozessor Bit rate Software Semiconductor memory Computer hardware Calculation Operating system System programming Error message
Presentation of a group State of matter Multiplication sign Demo (music) Execution unit Sheaf (mathematics) Mereology Database normalization Mechanism design Endliche Modelltheorie Information security Error message Exception handling Social class Chi-squared distribution Keyboard shortcut Mikrokernel Maxima and minima Sequence Virtual machine Data management Befehlsprozessor Process (computing) Interrupt <Informatik> Speicherschutz Physical system Ocean current Point (geometry) Web page Game controller Implementation Service (economics) Data recovery Student's t-test Event horizon Element (mathematics) Number Latent heat Read-only memory Internetworking Computer hardware Operating system System programming Software testing Interrupt <Informatik> output Booting Computer architecture Mobile Web Context awareness Operations research Pairwise comparison Interactive television Machine code Database normalization Event horizon Doubling the cube Software Personal digital assistant Computer hardware Cube Musical ensemble Exception handling Marginal distribution
Operations research Personal digital assistant Interrupt <Informatik> Mereology Physical system
registry or a control circuit or any other electronic circuit this may result in to memory corruption but since the component is not hardly or severely damaged the software may continue running smoothly on tip which rates from the part of the memory that was corrupted evaluation of commonly used CPU believe that tons of transient faults Mako's calculation error or program crashes so either the circuit Pervez program must be protected in my research we should to protect the program and precisely the program we are talking about here is the operating system and we approach we choose is to control the operating system education through a virtual machine this leads to this applicator where we have a hypervisor
running directly on hardwa and allow allowed us to control the Gaspar's we are using a combination of Nova and vecinos software with the use of virtual boss to control the operating system education in Doncaster as best machine general approach is to rely on a system
has great affection and recovery mechanism like margin check architecture memory protection facilities correcting code and errors which may remain undetected by Hardware mechanism we rely on double execution with comparison of short processing elements which lasts at most two hundred microseconds and executed atomically the problem now here is how we handle the currency of the system and the performance impact while we are executing redundantly this points of instructions and in the presence of external interrupts which are as the corner student to software to be protected here is divided at one time in a short process implement a processing element is as we said the sequence of posters TPU instructions but are delimited by either a maximum number of instruction which we detect this by using by triggering with performance monitoring interesting element may also be delimited by system called CPU exception like page fault general occupation world taxed state segment errors this kind of a section also he stopped the processing element when there is input/output destruction we push this switch and later will also rely on touch on much impacted to stop will processing element so all this event triggered posters in element stop so that we can realize a cube and compared with to as equation and detect if there are transient fault or not so concerning the astronaut interrupts we distinguish two classes of external interrupts the first class is performance monitoring monitoring interest this interact is used by the hardening model to stop the process implement when a specific number of instruction is executed by the CPU and this controllers have to be funded immediately the second class is all the other interests on all interrupts this interrupts cannot be part of the processing element the handling is delayed when they arrive if they arrive if they are triggered we killed them so they are huge so the first service team until the processing element is finished so when they arrive we until then we are secure and empowered and after permitting the current processing elements the people recorded interest in first-in first-out olive special care must be taken when during this special care must be taken regarding real-time processing required immediate servicing are not imposed in the processing element hidden potency written we may say Vistage directly or immediately but if it cannot satisfied describe it criteria this in this way we face a pacifist why we cannot hundred this kind of interact now truth test of this approach or know this habit of unit system with each microkernel Nova and the during during booting fists which last about six hundred people gigas occurred approximately four minute if no I don't do we noticed that 99% of all time also all other interrupts so it is a busy time and interest that were triggered during this routine face is party late especially time entered were delayed we were in average 18 microsecond keyboard or the global system in Europe where delayed with about 40 to 50 microseconds in average so this was the case when the system was booting when the system after the system boot completely we let the system run with either use and the other all we got was that only 20% of Tanjung Perak were delayed where he has none of the other interests who are delayed it is this is quite optimist as optimistic about our performance with jewel as the cushion of processing element because the current implementation is largely improvable and all the system after it's finished will run in in a after booting she's completed so in conclusion we may say that when a security redundant the sequence of instruction of piece of software internet management is the key aspect to performance here we should we choose to delete the service team to ensure that the two as the christian harvesting we investigate the performance impact and the system and we found that in general this will not impede the operating system your education in mobile as a christian so touch the conclusion we work in and that also end of our presentation thank you for your kind attention any question or suggestion all right Don thank you [Applause] [Music]
is your concept working consider multi-threading now so this will be part of future work so now multiprocessor are left for future investigation seems not to be the case so you [Applause]