so hi I will plant you spine annex VI

which is an alternative hardware description language for digital adware

so during this presentation I will first give you a little introduction about spending idea how it come how we can use how we can use it and then I will give some different ways we actually land very dog and then I will give you many little example to show you the invitation of spaniel HDL and how it is different what give you by using some abstraction and by using some software engineering approach to do hardware design so this position we okay this penetration will only be about since it is about hardware it's really not about simulation thing you can simulate the output netlist so yeah to simulate generated the hardware you can use regular tools because output netlist of Spain an Excel is reacted and very large so you can do the simulation of those octave netlist so yeah this is the

context I don't have many time to give you my opinion on that but basically what I think is vehicle chosen to and very luck 2005 are really bottleneck in terms of engineering by many aspect and vex dealt with an atan system very large will not save all of us because of idiot support because even of features that they bring that are not so good finale so I don't really have many times talk about that sorry but so finally clear it

is an open source project which start in December 2014 it focus exclusively an aerial description and as you can see here there is the flow so you can describe your hardware by using some Scala files then you ask it's a Spanish the compiler to translate it into a regular of the HDL and very lot that you can sensitize or similar and so chief mates spinergy directly compatible with all idea tools because its regular vehicle and very dark and you can also integrate some legacy IP like block from fog from hiding some from material you know are some more complicated things inside the Spinelli the spine and exterior key by using a black boxing system so it's quite compatible with existing flow and existing IPS then about the abstraction level it it starts at the same levels and we examine very dog a little bit different but the thing is then on the top of that you can build a new abstraction another you can go away from this mess of for your kids hardware design to really say what she wants so yeah just before example some last points so there is no logic of ahead in the chromatic cut because financially L is not a ETLs approach it's really much more like an LTL approach as we acted in paraguay you have to design gates what you have to design registers in six like that there is no other it you will not lose performance by using it all names and all your co-parent iake is pretty bad during the translation from spain lyrics they are two very long and via so you can simulate it by using your favorite simulator you can look at the wave and then very easily understand by understanding the wave catch-up where is back in Spain Yahoo f1 and basically expand a girl is not ready a language and this is the main point about venereal Spanish there is a language if it's a color library so scale is a gonna hurt purpose programming language and Spain Eric DL is a library implemented on the top of it to allow you to describe being new hardware and it could seem strange to have a language into another one but it is probably one of the one of the best point of Spain in a clear so I will come and touch later so yeah this is a simple example a very random one which has no interest in practically but imagine you want to design this little piece of hardware with a single condition to derive some comment or logic some register without reset summer Easter with roulette in VHDL and in regular because you have to use assimilation constructs to build hardware to interface a hardware because the Eglinton Parag were initially made for simulation purpose not for inferring Hardware so you'll have to write three different process you have a lot of redundancies because for example this condition is duplicated three times which is not very clean which is not really safe because you can create bugs by hitting duplications at many place so this is how you said to do and this is how you can do with an odd ready ticket at syntax and this is some finally clear example so first difference you can define things explicitly as signals like my register is a register not because you are as I need it in two o'clock at process but because you define it directly at the definition I want a reg of tip data type I want a reg of this data type with a reset value to zero so because things are explicit now you do not have to write process and these kind of things and you can write for example that you want nice enough to be forced by default and then when the call is true then you can assign all of those guys in the same conditional statement so another little example different is to compare and is to understand subtract another finish their rights that though if you want to define a simple timer component as you can do in VHDL and Verilog it's very similar like you can define yeah it's based on scales oh it's much closer though to software design in terms of syntax can define at time a class with some construction parameters this is like a generic or a parameter in very large then this class will extend component to say this class is a component so it's a logical element of my design then can you find IO into input/output into a bundle bender is a concept of hardware data structure and spinal area then can define inputs and output of your components it's very easy then can you find a counter into ensign your timer which is a register of this data type then you can write conditions as I need all the conditions reassign it so last assignment wind the last a figment win like in Vienna very large sign can do assignment so if you know how to do the again very long it's not so far you can use it by the same way excuse to not have to care about process and things like that but then I would start with the fun stuff so imagine you want to have a inject bits of color so behind chick bits of color I mean a stream of data which carry color of like a valid an already flag as a patrician and payload as an idli be data structure and okay you have a source and check this of color you want to cue it inside the FIFO and then you want to connect it to the sink and check this of color so in the air 2002 it is really kind of boring because you have to define Exynos one by one in many cases you can not really use recorder because you want to have them permit rised by verax so you can't really use records there in all cases then the most boring part is probably about instituting the component itself where you have to paint evening nails one by one which is very error-prone which is very copy past work which is I don't keep work maybe so in Spain like the sinks are much more object oriented which mean so yeah for example if you want in Spain out there the concept of handshake this is named stream so if you want to define a source stream and a sink stream you say I want a source and a sink which have stream of RGB color with this parameter addition so you can already much more use that a stricter with which have privatization we have in a parametrization you don't have you are not bound at this level and assistance to entry twin so it is 5 for you you say I want a 5 for a stream FIFO with this has element which are very faithful you don't have to be in all signals of you that has tricked you into a single se the basic vector anymore then you say the depth that you want and then this is the thing if you want to access the first part of the FIFO you say five for that I owe that pash you don't have to be in sync you directly have access to them by using lit kind of object-oriented way like a FIFO is an object you can say I want to access this attribute of the FIFO then here for example it's written that you take the source stream then you connect it to the back part of the FIFO and here it you take the top part of the 5:1 you connect it to the sink so it is better than this already but it could be better and I will command better way to do it so basically stream is not something that come magically from Spain excel compare oh it's something which is implemented and the top of it by using regular syntax of it as painting a clear so it is a class with a type parameter here which extend bundle because this class represent and have a data structure so a collection vendor then you can define element into your data structure has a valid fagged and ready flag a payload instance of this permit feasible type so you can use this data structure has a slave input of you component or as master output of your component it's not like records where you have all signals that can only be in one direction it's not explain how to do that but it is very useful and easy to do and then there is this thing this data structure you can add functions in functions in it like the operator that we have seen there to connect you trained in in vehicle and very dug function tasks in procedure are not that much useful because inside them you can't define what you want you have to define rare relationship between outputs and inputs of the function but you can define inside them register you can insulate a component you can do all the tricky stuff that you want you already limited with them but here you can

really do what you want like can define a cue function we take as parameter how many big you want the cube to be and then this function we create for example a new FIFO internally and you cop an answer and then it will connect as a stream on the one who you are cutting it to the perfect part of this five four and this one can read wrote on the

output part of this FIFO so it is really simple but in fact there you go in place of writing or T stuff is already better than regular VHDL you are just writing tips like you want a source and a sink stream of RGB colors and then you'd say you take your source you want to cue it we are 5'4 of sixteen element and then you connect it to the sink and there you are starting to going away of the mass of fire of other word design you are saying what you want and this is working you can you can write a blog like in that you can do mistake in your wiring you can do these kind of things so it's it's not only you can go further then like imagine you want to do this ad where like you have a saw stream of color this is our random example but it gives an example imagine you have soup handshake I saw stream of Korea you want to draw a section of this stream when they are black so you need to add these arbitration gates and this check then from this point you want to add a pipelining stage to have better maximal frequency or 12:1 depth five four three eight I don't know so you need to add that so anywhere probably if you have to do that we do it by hand and it's really our province it's if you do arrow inside bit pressure and it's always a lot of time to find out where is a bug in your arbitration but here there is how you can do it in Spain HDL I mean how you can do it by using the library which is intimate on the top of Spain in exile like you can define a so stream of every bit color then you can say I take my school stream i want to throat election when the sauce payload is black and then with this function through and we do it on t stage till this point and then you say i want to stage it and t stage function we create this ad where for you and then it returned t's just not and then you name it sink so really you are you are saying what you want and not how really it work signals by signals and this is not magic here you can do you can navigate this to the implementation of this function and this is pure RTL and limitation it's not from this panel compiler so another example thick machine so you can design sick machine as you do in reactant and very large by using switch statements and things like that but you can either use the state machine tool so state machine tool is one time again limited on the top of spinner deal it's not something integrated in it and if you want to do two state machine though you can say I want a new state machine I want state ABC which are States state a is my entry point then you can define some signals inside it and then you can say state B on entry I want to set my contour to zero state B when it is active I want to contact when my container is for I want to go to state C and then instead be when it exits I want to put my eye or vessel to true so it's just an exam that's Spanish they'll allow you to rise your level abstraction but it's not because it's implemented in it it's because it's syntax is flexible enough to allowing you to build this abstraction state machine is not magic really it's just software engineering with how do I design combined together so another example imagine you want to do that you have apples like a Naxalite or pb-1 I don't know then you want from T's boobs be able to drive a signal a and B which are inside of 32 bits so you want to have some register here which right only from T's B's then you do some calculation like multiplication between both and then you want to be able to read the result from this booth so if you want to do that in via control log we have to let to manage the these timings by hand to do some switch cases so it could be a right but it's not the only solutions so here is an example if you want to create a next slide for this you can write it like that and then you can use an next slide slave factory tool the TSP is one time again content at the top of spin excels not integrated inside it and this tool will allow you to specify you register mapping by by in an abstract way without having any an acknowledge of the boost timing then like you can say a is something created from the factory as a right only register of T's data type mapped at this address and the same for B and then you can do some calculation here with result and then you can say I want my factory to make the result readable at the address 8 and this specification here is completely abstract from the fact that it is a Naxalite one you can replace it here by a PV one and it will work directly so and behind that there is a lot of software entering like there is ash map that you can use to elaborate your design and this is used behind the center there is abstract classes there is abstract functions there is irritancy ever eaten see ya every new in every tense exactly yes there is many things that you can do so a last example this is list at the most Russian project that has made fully in Spain there used to check that each worker Ecklie and it's not too much buggy and this is a kind of little SOC which work on SPD a with an risk 5 CPU with instruction cache avatar chained to debug it some as their arm controller from a pity bridge for low performance peripherals GPIO timer you at Nvidia this is an acci for interconnect is in a PB interconnect and there is some simple card which are interesting inside it like for example to implement to fun / - instance here it is a PB bridge from AK see like from occifer it's just writing that you say I want my bridge with this parameter section and T's it's done and to instantiate or this decoding stuff for a PB with all those connections between components if you're saying I want an APB 3d color my master is a people bridge IU a PB and there you can give a list of safe like timer controller I / PB is mapped at this address with this address range and you know it's in fact that it's in very dark is it so boring to do that so here it is saying what you want and you get it then there is another pattern though it is for the exit for outside and this one use a data model pattern like you can

create an acci for crossbar factory then you can fit it with some data model by saying I've this list of slaves on up there you have T's lift this list of master and they can access to slave and then you say I tell you everything please build yourself so you can really do software engineering to design your hardware with this approach and yeah since this is all for this presentation about spinning idea you can find everything open source in this repository there is unlike the combat we can't start with a good I think there is I'm ready to use project to help you if you want to try it and some communication channels or do not hesitate to to comment them if you have some issue to start up with tools or anything so this is all thank you [Applause] sorry to compare it with chisel so basically I stopped to work with hazel I was happy some months with it that plus two years ago and or two years ago but basically it appeared that there was a lot of issue with it and like for example clog the main support which was very badly done and there was regularly some issue about it but no no but there was no move on the kaiser stuff so you can also find a list of things that I don't agree with hazel in the design on the FAQ section of the an idea comment section and yeah maybe hazel is much more about a very large implementation of the idea has been like that it's much more about a V actually an intimate action of the idea which is with check more things and more stuff but really it look like interface is the same but really there is many differents behind the same like I have to check the FAQ so basically yeah how to to map some puce color into hardware it's your question like using hash map and things like that so you if you can writing software and make it able to work in hardware and software no it's not the case so spinach Dell is not an actually as approach it's really an ethyl approach where you use color as an elaboration tool to design what she want by saying among this register Monte's register i want to do the separation but Spinelli is not about translating and algorithms into other it's much more about saying what you want explicitly and you get it but you can use a sh map to do the version of your hardware you can use all these kind of things like dynamic list and but has an elaboration tool like a for generating vehicle or if the generate in VHDL this kind of things yeah so how I specify a clock for a flip-flop though manically it's much better than uvx debt because it is implicit so you can define area of your design which window the effect of a given clock and reset configuration and then everything inside it all sub components will automatically get it so yeah I had a slide but haven't the time to talk about it so whichever message you get when it doesn't work so medically you have much more confidence when you hear it spinning like the not least you have much more confidence than it's working physically in for real than handwritten VHDL one because finally I do a lot more check by default than seen we do a lot of check druggies and like for you don't believe check that you don't have come into a loop see we check that you don't have with mismatch these kind of things and if you have an error it will print you wherein you're spinning the description there is something wrong it will give you the name of the sinner so really it's maybe even less Easy's and the idea to remove bugs from a spanish their description because yeah i made so it check a lot of much more things and i put a lot of intention to have nice pretty aramis edge with the print stack of the execution of spain a little description and these kind of things so it's not really messy it all right have to try to give like to get a good idea of it I can some of the questions be put in these discussion session uh you know try to be quick question so there will be three process limited from it exactly like they're exactly the same yeah sorry Oh spending like that all is how did this thing is in between blocking and not blocking so yeah in Spain like there by default it is I don't know which is one but it is like the default but like this one here yeah you can do the other one by using another syntax - so how the mission is

translating to react they're exactly the same sign in VHDL so then if you want to use I speak here dedicated blocks and things like that you can associate a black box or you can try to write it by the way that the synthesis tool we in the stand it's that but there is no magic between in the translations oh it's one to one so if you to about from a rebuking between the input spiny tail and outputs there is no formal verification about it because basically it's not work yet because you are verifying the outputs at least you are not doing your verification stuff on this binary the description you are verifying the exams related files so it's why I don't really

care about it being formal but I have a good confidence in the translation process