WIRELESS VILLAGE - RFNoC: Accelerating The Spectrum with the FPGA

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WIRELESS VILLAGE - RFNoC: Accelerating The Spectrum with the FPGA
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Talk will focus on privacy (or lack thereof) of gotenna networks. We will cover traditional attacks which have only been available to state sponsored prior to popularization and wide availability of software defined radios. We will cover signal analysis, triangulation, protocol analysis, deanonimization, cryptanalysis, spoofing and selective jamming. Since the gotenna ecosystem also includes an app we will cover the vulnerabilities in the underlying crypto libraries, weak token generation, broken API segregation as well as other vulnerabilities. You too can learn how to analyze, snoop on and exploit RF networks like a pro with a hackrf, laptop and some elbow grease, sweat and sleep deprivation.
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good afternoon everyone i'm neil Pandya and i'm nate temple and we're with that it's research and we'll talk about RF NOC accelerating the spectrum with the fpga so just a quick background about
Edison research and it's research was founded in 2004 by Matt ettus and it was acquired by National Instruments in 2010 and it's located in Santa Clara in California and his research makes software-defined radios they're divided into four different families the B Series the end the X and the E series and generally speaking the B series of radios that connect to the computer through USB the N series connect through Ethernet the X series connect through 10 Gigabit Ethernet and the ECU's are embedded radios ok and so most radios
software-defined radios connect to a computer directly and all of the processing for the radio occurs on the CPU and that's shown in this graph in this diagram at the bottom where we have a flow graph running with a waterfall display and all the calculations for that waterfall are being done on the CPU inside the laptop and people have tried to accelerate this data flow and increase the throughput of applications like waterfalls and increase the data rates between the radio and the CPU and one approach has been with the general-purpose processor and Cindy instructions so libraries like Volk engineer radio if you've heard of Volk vector optimized library of kernels and so their assembly language primitives that optimize the the DSP processing on the CPU and that efforts been very fruitful but there's still more that that would be desired and so the GPU has been used and there's a program called foster that we'll talk about in a minute that uses the GPU but the GPU has its own set of limitations doesn't always match well to a lot of block based SDR signal processing and it carries with it a high latency penalty and so the seat the GPU has had limited applicability to general-purpose SDR processing and so the other thought was to use the FPGA that's inside most of these radios on the edges research radios every radio has an FPGA inside of it so the thought was why don't we use the hardware to accelerate our processing and so the FPGA on the on
the other radio performs all the high rate processing like up conversion and down conversion and it's kind of the brains of the radio it controls all of the ADCs and the DAC it manages communication with the host computer and the code for the FPGA is open source at edits the driver for the radio is open source as well as the FPGA code so everything is open source is hosted on get on github it's written entirely in Verilog and these are the FPGA is used
on some of the different u.s. RPS the older gentle us are peas from way back in the day and they were much smaller the gen 3 III 10 and X 3 10 FPGAs are a lot larger the x3 10 is the largest FPGA that we have and it has a lot of space available for custom custom signal processing and we use go to radio with the USRP and we've integrated a way to use the FPGA and do FPGA processing from within the new radio and we'll talk about that we'll go through an example to show the motivation for using the FPGA and we'll look at Welch's algorithm for power spectrum estimation and we'll look at an example where we have a u.s. RP source block in the corner and this is a GU new radio flow graph taken from GRC and samples are coming in at 200 mega samples per second and then being processed in that chain with an fft complex 2 magnitude and then a moving average all of that processing is being done in the host and so the host computer has to ingest samples at 200 mega sample per second so 800 megabytes per second it's a lot of it's a very high data rate and then process those samples and do all of this math on every single block that comes through some of the math and a lot of these algorithms can be parallelized so in the case of the FFT that's a natural choice to move to the FPGA and so we may want to do that the transport between the the radio and the host is already pretty saturated then the host is already spending a lot of CPU cycles ingesting those samples and so we can alleviate some of the burden by moving some of the processing to the FPGA in the case of a full rate 200 mega sample per second stream that 6.4 gigabits per second processing and reducing the processing is one reason to use the FPGA but there's another important reason and that's latency a lot of algorithms cannot be implemented or at least cannot easily be implemented using just host-side processing in 802 11 in Wi-Fi you have the safest timings in Bluetooth you you have some other very challenging response times and you can't meet those where the samples have to go from the radio to the hosts go through the whole stack in the kernel and get processed by the application and come back out again and so you have to use the FPGA for a lot of applications so it's not just throughput but it's also latency these are the different
hosts sorry the different interfaces that the host computer can use to connect to the radio and each has their own limitation in terms of throughput and the even the fastest 10 Gigabit link is limited to about 250 mega sample per second and so if you saturate that link the host will struggle to keep up with all the samples that are coming in and even using a really wide link like 10 gig Ethernet may necessitate the use of the FPGA and so since the radios have
big FPGAs and this one here pictured is the x3 10 it has the largest FPGA that we that we use on the radios why don't we use it well it's FPGA programming is
difficult it's very different fundamentally from C or C++ or Python or host-side processing has anyone programmed in Verilog or VHDL before there any FPGA developers out there ok so I'm sure you'd agree that FPGA processing FPGA programming is is fundamentally different from the host and not everyone is familiar with it and there's a learning curve to get up to
speed a lot of times when you have a design team there's three domains you have software experts who are experts at implementing something in Python or C++ and so on your new radio perhaps you have algorithm experts who might live in the MATLAB domaine and focus on on the math and the algorithm itself and the performance of the algorithm and then you have FPGA experts who are experts at fitting a design into an FPGA meeting timing and building hardware to do the tasks and a lot of times those domain skills don't overlap and so it's FPGA development can
be hard and time-consuming and so the goal with RF nock is to make FPGA acceleration more accessible it aims to provide a way where you can write an hour if not block to implement your logic your functionality and insert that into the framework and let the framework take care of all the glue logic and all the data processing all the data handling the data flow and integrate that into the host so that you can use the the api the api for the radio to control and and an operator or logic your block and in the past the FPGA is were we're more monolithic and you'd have to look at the entire design and figure out where in the design to put your code but with RF knock the goal is that you can use the framework to handle a lot of that plumbing for you and really just focus on your own application RF NOC is GPL and specifically LGPL and so the modules that you write you do not have an obligation to release the source code to those modules it's fully integrated with your new radio but you do not have to use the new radio you can also use RF NOx from C++ so if you're not even using for Guinea radio for some reason a lot of stacks don't use Guinea radio like the cellular stacks open BTS and SRS LTE and so on don't even use it and so if you're not using it that's fine or if not can be used from C++ as well this is what the architecture looks like at the bottom you have the the FPGA domain and the dashed red line is the boundary between the host and the FPGA on the FPGA you have a a thern ette Mac interface and this is the the block that interfaces to the 10 or 1 Gigabit Ethernet interface to your host computer and then there's a crossbar the crossbar is a packet-switched crossbar basically a switch a network switch which is where RF nut gets its name RF network on chip and so packets of IQ samples switched or are routed throughout the chip and through the crossbar and from the crossbar all of the blocks are connected and whenever a block wants to talk to another block passed samples to or from another block or plus passed samples to the host computer or receive samples from the host computer it goes through the crossbar there's a radio core block which represents the interface to the transmit and receive chains and takes care of all of the plumbing and all of the interface to the radio and then there are these computation engines or more commonly known as just RF not blocks and this is where you implement your logic whatever that might be a Viterbi decoder or some other function I just said that that the FPGA connects to the RF front end it controls the the functions of the radio and the Ethernet interface is not just for Ethernet there's also other interfaces supported as well like PCI Express the RF knock block is something that you can ride or you can get from from other sources I'll review that in a minute and the crossbar interconnects all of the devices on the FPGA on the whole side the UHD driver using the RF knot framework allows you to configure your block and use your block and provides an API to control and access your block from your C++ program or you're gonna radio flow graph and you can do that in C C++ and Python or in canoe radio which under the hood is C++ and Python so look at an example of plotting spectrum the radio core is now represented by that block in the top corner of the RF NOC radio block notice this is still good new radio but the block names have changed because you're now using blocks from the RF NOC library and so that library provided by industry search when you install it in Senshi AIT's all these different blocks that are on the FPGA it's a little hard to see but the lines between the blocks now become green and that indicates the data flow between blocks is on the FPGA and not on the host and let's say we have the radio core sending samples onto the host and so we have a RF knock radio core block on the left and then a dashed lines a little bit hard to see but that that arrow between the radio core block and the stream to vector block is dashed indicating that the dataflow is crossing a domain boundary it's going from the FPGA to the host and then the rest of the processing right now is on the host and say we want to move the FFT to the FPGA to accelerate it and so we replace that fft block that's being run on the host with an RF NOC fft block and notice the arrow between the RF NOC radio core block and the fft block is now green again to indicate the data flow is on the FPGA and so now we have an fft block and the data flow would look like this the radio core receives samples the samples go to the crossbar they're routed to the desired block in this case the fft block and then the fft block performs its function it's FFT and sends those samples out back to the crossbar and they're routed to their destination which in this case is the host computer and the rest of the processing in the chain in the flow graph occurs on the host computer if you want to move additional functions to the FPGA like the logarithm or whatnot in this in this flow graph you can do that
and add additional RF knock blocks this
is what the are the blocks look like when you zoom in a little bit closer all of the the communication between blocks is packetized and so there's a packet Iser and a d-- packet Iser in every block and all of those those modules in green are provided by the RF NOC framework you don't have to write those and so there's a packet Iser and d packet Iser to packet eyes IQ data sample data from the radio across the crossbar and there's a FIFO for flow control the FIFO also serves another purpose for clock domain crossings I'll talk about that in just a second and then there's a TX interface and an rx interface that controls communication with the rest of the radio and in the example from before from the previous slide samples are coming in to the radio core block and being received they go to the crossbar and then they come in to the FFT block where their D packetized again there's a FIFO for flow control and then they go to the to the FFT itself which is in the pink box and that can come from any source you could write that yourself it could come from Xilinx you could get it from open cores org or or wherever and the only requirement on your law is that it uses AXI streams and there's a slide coming up where I'll go and a little bit more detail about AXI but it's an industry standard for a point-to-point link between modules and most IP out there third-party IP like from Xilinx supports AXI so as long as your IP speaks ax e if you would you can insert that IP into the RF Na clock in the pink box here and connect it to the rest of the framework and I said that about these these footnotes here I already said and where do you get this IP let me fast forward for a minute
actually I'll not fast forward and let
me go to a different example so look at
a cognitive radio example this is this is a hypothetical example where we want to do some cognitive radio and control a lot of it from the FPGA not just from the host and so the radio core perceiving samples and that goes to the fft block which comes from say Xilinx an fft is calculated and that spectrum is sent to the spectrum policy block which could be some kind of soft processor or some other kind of logic that maybe looks or energy in a bin or some other criteria to determine that something is happening in the spectrum that we're interested in and then when that happens a trigger is sent to the TX modulator block and when that block sees the trigger it downloads or it receives it requests a payload from the host computer for samples to be transmitted and it goes and transmit those so this is an example of RF knock an application of RF knock and notice that all the blocks all the RF knock blocks that are added and orange don't have to come from the same source in one case in this example they're coming from Xilinx in another case they might be coming from Favaro HLS I'll talk about in a moment or they could be something that you wrote yourself or you you took from open cores org the blocks can come from all these different sources like I said you can use the built-in industry search library when you install our if not there's a couple of blocks that come with RF knock I think there's about 14 or so right now and they they support all the common DSP functions like FFTs and Windows there's a sig gen blah there's a bunch of blocks that come with the framework you can of course write your own in verlag or VHDL most of the tools or dual language tools these days so you can use either language you can use open chords org which is an open source repository for hardware and obtain a block from there you can use third-party IP from Xilinx you can use Vivaro HLS which is a tool that will generate a ver log in VHDL from a C++ module so if you not interested in coding C++ or sorry vera log v-tail from scratch you can use that tool to generate the Verilog and VHDL from a C++ module there was a challenge that we ran last year with Xilinx and three teams were selected and they their code is available on github so if you're
thinking about using Vivaro you may want to look at their code it's all posted on github and they I don't remember all of the three projects I think one was ATSC decoder but they implemented three different systems using Vivaro HLS and so there's C++ modules that that generated RF NOC blocks and there's also HDL coder from the math works where you can take em files or semi link models and generate ver log in VHDL from that when you build the FPGA for use with RF NOC there's a couple of tool chains the older radios use ISE and those radios don't support RF not our stock is only supported on the e series that the X series the X 310 and the N 310 and three hundred and a use Bovada which is the current tool chain that that Xilinx supports if you're using the e 310 or III twelve you actually can use the free webpack Edition and so you don't need a license you still need a license file but it doesn't cost anything but the newer the the larger FPGA is in the X and n series and 300 series do require a paid license and you would you install Xilinx once you had Xilinx installed you would build an FPGA from the command line we provide make files in the UHD repository when you when you install RF knock and you invoke the build process from the command line there is an optional GUI as you see in the bottom of the slide there's an optional GUI that you can invoke and the GUI is basically a wrapper for the command line so you can use the GUI to click through and select what target you'd like what blocks you want to add to your design and then go and build a design this is what the GUI tool looks like you select a target on the left you provide some edits blocks on the middle you bring them over to the right side to show all the blocks that are in your design and then you generate the bit file you generate the FPGA image and it'll show you the command line that it's going to use to generate that and you can take that command line and copy paste it into a script or invoke it manually on the command line if you prefer or the tool can just invoke it directly the GUI tool can invoke it directly and with that I'm
gonna we'll talk next about fostering I'll turn it over to my colleague Nate so many of you are probably familiar with an outer tree module for the new radio toolkit called gr phosphor it's one of them it's an emulation of an RTS a like spectrum visual visualization gr
phosphor originally gr phosphor was designed to run on a GPU using open C on OpenGL for acceleration it's great for fast signals and if we look at the demo that we have running here it's we're looking at Wi-Fi and Bluetooth there so really short intervals there's also an RF knock variant now this the what's running is the RF knock variant it was creating my sylvain movement you can find them on Twitter at TNT and on the Osmo comm wiki pages and along with an additional video demo of phosphor so
this is a GPU phosphor which you're probably familiar with this is running with ABI 200 so I'm looking at 50 mega samples 50 megahertz worth of bandwidth at a given time on the left here this is a bunch of push-to-talk traffic police Fire EMS type you know business radio type stuff then we'll see LTE various LT channels along with a pair of WCDMA channels there now this is all being processed on the host so the CPU has to bring in the samples and shuffle them off to the GPU or then the FFT and processing is done which can be challenging it works for 50 mega samples like a the new nvidia z' 980 s will do 400 mega samples or so through them but at one
point to make the data transport rate across from the radio to the horse host is 1.8 or 1.6 gigabits per second at 50 mega samples this is also a 50 megahertz
view of the same Center frequency however now this is the RF NOC version instead of running at one point 6 gigabits per second the transport rate from the radio until to the computer is around 4 megabits so it's incredibly an incredible reduction in the bandwidth that's required for that one interesting note I want to make about this screenshot kind of a little historical neat thing if you look in the middle
there there's a peak there's several little small Peaks there between the WCM chiong channels and the LTE channels and here they're gone
radios sitting in the same spot or the antenna sitting in the same spot but they're gone where do they go these are anybody you have any idea what those missing signals are if you guess GSM that would be right and so this this
screenshot is from before January 1st 2017 and this is after 18 T shut off their gsm RF knock offers the RF NOC
version of phosphor offers various shadings so here's a few views of those
now this is the same Center frequency but instead of looking at 50 megahertz worth of bandwidth we're now looking at 200 megahertz worth of bandwidth and
this would be at if we order be streaming the 200 mega Hertz over to the host that that's a six point four gigabits per second but even though that we're now doing this on our effect this is still at about four megabits per second so it's possible to stream this over the Internet so here's an example
of a Wi-Fi channel and you can see some Bluetooth I think there are a mouse or something a little NFR 24 modules so
this is an example of the RF knock flow graph starting with the radio block on the left if you note as Neil mentioned the green lines that are in between the blocks indicates that that data is being transported on the FPGA between the blocks so first we're bringing in in this example we're bringing in 200 megahertz off of ADC and then we're going to go through a DD C so is the digital down converter this is a decimation stage it within the FPGA so it's gonna bring it from a 200 megahertz rate down to a 50 megahertz rate then we run an FFT windowing function I think in this one we're running like a Blackmun Harris next we go through an FFT which will come compute the Fourier transform next it goes into the RF knock phosphor block and this will actually take that vector of bins and generate the visualization that's sent through a couple FIFO for buffering also through a copy block once it's under the hosts for additional buffer and then on to the actual phosphor display block which is what you actually see and that's see one
of the only things that's running on the host this could run on a Raspberry Pi and in comparison if you want to take in a 200 megahertz sample stream need to basically a high-end i7 CPU just to be able to keep up with it this can run on a Raspberry Pi so we're currently running the demo here in Wireless village to provide spectrum monitoring service for the wireless capture flight contest there's a physical knob that is on the desk and Neela's gonna pick it up and hold it you can come up and you can tune it around and if you press it it there's predefined frequency so you can hop around to some interesting looking signals so right now we're looking at 2.4 and if you click it a few times you'll hop around you'll find the you know 700 megahertz LTE and various signals come up and play with it twist it if you press and hold it it will adjust the game so you can turn the gain up and down right there so in summary RF knock we're trying to make fpg acceleration more accessible this doesn't mean that if you don't with an exception HLS with evaldo HLS you're able to convert C and C++ into the VHDL or Verilog code and but if you don't know FPGA paralog or VHDL there's still a barrier of entry slightly it's not a fully automated framework like you do have to understand a little bit about FPGA development it's tightly integrated with your new radio but you do not have to use a new radio you can use it with you know C++ and pure UHD there's a built in block or library or blocks for OFDM FFT for filters signal generator the phosphor blocks those blocks are all portable between all the usurps so if you develop something on an X 300 with some slight modifications possibly you can port it to any other system generally if it works on one I work on all of them it's completely open-source as anyone mentioned so in licensed under LGPL which means that you do not have to release your IP if you choose not to we have a knowledge base that's at KBS calm there's a great getting starting guide there's also a companion video which will walk you through building your first RF knock block just a little plug there's a new radio conference coming up it's in Las Vegas or in Henderson this year we will be running three four-hour workshops on our FAQ which will completely go through and you'll build your first FPGA image and running we'd like to give an exceptional and a special thank you to first and foremost 0ks and rick melodic and the entire wireless village crew the service that these guys provide is outstanding it's pretty rare to find a group of people who are so dedicated and so thoroughly
interested in teaching the world about wireless security as soon as you take your data off the line and you put it in the air it's free for everybody to take there's no there's no security you have to in a lot of times our security is overlooked also I'd like to thank the Corps RF NOC developers and architects
Jonathan pendulum and dr. dr. Martin Braun they've they have architected and built this wonderful framework that is making it much easier for you to put your custom DSP into the FPGA thank you for coming I appreciate everybody's attention and that's it would you like to have anything last words [Applause]