Realizing functional, useful quantum computers requires that the research community address both fundamental and practical challenges pertaining to how hardware errors are suppressed to tolerable levels. In this talk I will focus on efforts towards the development of dynamical error suppression as "quantum firmware:" protocols that are designed to suppress hardware errors at the physical level. We introduce an efficient, experiment-friendly filter-design framework for understanding the performance of various pulse sequences, making connections with familiar concepts from electrical engineering and digital signal processing. This perspective allows a concise formulation of known sequence characteristics, but also reveals previously unappreciated practical impacts of system-level constraints. In addition to studying dynamical decoupling, we extend this approach to nontrivial logic gates, providing a simple new technique to calculate and suppress hardware gate error rates. We validate the filter-design approach through experiments using trapped atomic ions as a model quantum system. Our results reveal the performance benefits of optimized dynamical decoupling sequences and demonstrate a technique for sequence optimization through multidimensional search and autonomous feedback.