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End-to-end formal ISA verification of RISC-V processors with riscv-formal

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without being next part is called in an informal and might verification well risk by process there's with risk by formal I have no idea what this means but I'm very excited to understand what it means and and Clifford promise he's going to make sure everyone wealth on Clifford has been very you know in the open source and free software resources of my gosh free and open source and community and especially he's known for the project I store and please help me welcome Cliff the thank the so the the the I the yeah yes yeah the yeah the is 5 is
an open instructions set architecture to mobilizing so it's not a process of but it's a process specification and eyes a specification that is free to use for everyone if you happen to have already implemented your process at 1 point in time you might know that it's actually much easier to implement a process of them to implement all the tools that you need to compile programs for your process and if you use something like risk 5 then you can reuse the tools that are already out there so that's great benefits Highland for this endeavor we need processes that actually really compatible with each other processes that implement there is 5 is a correct so with many Elysees we start with 1 processor and say 0 that's the process and later on the figure out there was a back and what people sometimes do the just change the specification so that the specification of fits the have that actually have we can do something like that the 1st 5 for the many many implementations of they're all being developed in parallel to fit the same specification so we want to have some kind of means to make sure that all this process as actually agree about what year are my is a specification S so lots
of formal verification from eradication is a super brought time on in the context of this talk and talking about how the model checking more specifically I'm talking about that it's taking of so called safety properties so they have some how the design and we have an initial state and would like to know if this habit assigned can reach the bad state from the initial state that's of formally the problem that you're trying to solve the arm and that to 2 means to do that 2 different categories of proofs that bounded and unbounded proofs and that the bounded proves the only prove that it's impossible to reach a bad state within a certain number of sites so the different maximum bound for the length of a counterexample and with unbounded proves the proof that a bad state vector never be reached so I unbounded proofs of course better if you can make an unbounded prove and that in many cases this is very hard to achieve and that bounded process something that we can do so and so and talking about the proofs here and for the most part so what's the
end to end formal verification are because of those entitled as historically when formally verify something like a process and you break down the processing in many small components and then you right properties for each component and proof for each component individually that they are adhered to the properties and then you make a more abstract proof that if you put it system together from components that have this property that this system that have 2 properties that you want I with end-to-end verification of the their processors 1 huge black box and just ask the question does this 1 huge saying the polar specification have the properties that 1 and it has a couple of them the just and it's much much easier this way to take 1 specification imported from 1 processor to another because we don't care about how the process statement on the on and it's much easier to take the specification that we have and actually match it to other specifications of the ICA because we have a specification that says what is the old behavior we accept expect from our process but the big disadvantage of course that is computationally much more expensive to do end to end of formal verification on and doing this end-to-end verification of a processor against my eyes a specification is something that historically was always few as like a textbook example of things that you can do a formal but fortunately this they became much better in the last couple of years and knowledge you use the right tricks we can do stuff like that of a 3rd of the soul was definitely so this
risk by former risk by former is a framework that allows us to do and to and formal verification of risk 5 processes against a formal version of the eyes a specification so is platform is not formally verified processor is that if you happen to have arisen 5 processor you can use rest 5 formal to prove that your processor conforms to the eyes a specification i'm for most part of this is using bounded methods theoretical you could do and bounded proofs with respect for almost but it's not that the main use case I'm so it's good for all of the caller back hunting because maybe there is a counterexample that would show that the process could diverge from the desired behavior of a thousand or 5 thousand sites but usually when you have something like a processor and are you can reach a bad state within the very sharp bounds and you have a high confidence that actually yeah process implements the Isaac correct and so if you have a process and you would like to integrated with risk 5 formal and you need to do 2 things you need to add a special traceplots clear processors quality RV of light transport risk by formerly interface transport I'm and you have to consider its performance of this platform understands the of the the attitudes of your processes of example is 5 our is of a labeling is headed to bid and 6 the folded Russian yesterday was performance if you want to verify a 32 bit or 64 the process of risk 5 is a model of Isaias another a couple of extensions and you have to tell risk performance which extensions your processor actually and implements right and then that a couple of other things that not transparent for a user land process on and like if I underlined loads of are supported by the heart native because risk 5 despeckled assess our that they to an unaligned load or store than a user space program can expect this load or store to succeed but it might take a long time because there might be a machine interrupt handler that is emanating and unaligned load by doing aligned loads and stores the and but if you do this formal verification of the processor then the year of risk by former framework must be aware of what is the expected behavior for the cause for the fact that season unaligned lost all shouldn't just perform the load so what does this interface look
like that you need to implement in your process so if you would like to use was performed this is the current version of 2 risk 5 formant interface on the right now there is no support for floating-point instructions on and there is no support for C is ours but this on the 2 Buddhas also this interface will grow larger and larger than the and this additional features but all of these additional features will be options are and 1 of the reasons is that some might implement just smaller microcontrollers that they actually don't have floating-point cause or that don't have our support for their privileged and of specifications so that don't have c is always and through this interface whenever the of retires instructions it documents which instruction it retire so it tells us this is the instructions about I retire this was the program counter they are found instruction is the program counter for the next instruction is other registered for the rat and these are the values that I've all after the register file this is the register left Britain and this is the value that I've written to the register file and all that stuff so is short what the document through the risk 5 interface is but that part of the process of state that is observed by an instruction and the change to the state of the proteases that this performed by instruction like changes to the register file or changes to the program and of course uh and most process is actually a superscalar even those processes that say that non superscalar in all the pipelines really can do stuff like like retire memory load instructions all the although in parallel to another instruction but that does not write the register the things like that of so even with the with processes we usually don't think of as a superscalar processors even with those processes we need that the capability to retire more than 1 instruction each cycle on and this can be done with this and red parameter he order ports on up like 5 times wider life and red is is 5 the the the but he's about to have a process so
that implements this interface are what is the verification strategy the risk 5 of formal of furrows in order to do this proof from reverify that our process is actually correct so there is not 1 big proof that Iran is that there is a large number of very small proofs of that you are this is like the most important trick of and encompasses and that 2 categories of proofs out 1 of our categories like already instruction checks but we have 1 of those proofs for each instruction in the eyes a specification and each of the channels in the risk 5 formant and so this is easily a couple of hundred proofs right now but because you usually have and instructions and if you have like 2 channels or is it 200 proof that you have to I and when this instruction checks do they are reset the process and of other the symbolic state if you would like to run of a unbounded prove on let the process run for a certain number of cycles and then assumes that in the last sighting on their our process of retire certain instructions so if this check checks if the box correcting it assumes that the last instruction retire than the last psyche of the checked of B. and add instruction and it looks all and it looks at all the interfaces on the rest 5 formant the on to make sure that this is compliant with an and instruction in check SIFT instruction is decoded correctly it's a text if the register value of the right to the register file is actually the sum of the values in red from the register file and all that kind of stuff on well of course is to just have this structure checks there is still a certain verification gap but because the core might like to us the core might say all I write this value to the register file but then not right develops the register file so we have to have a separate set of rules that do not look at the entire was 5 formerly interface in 1 cycle but look at only a small fraction of the risk by former interface but always span of site so for example there was 1 check that says if I write the register and that lead their read the register I bet the read back the value that I've written to the register file and that is I call consistency checks and yes so
that's I think what accelerating on
so for each instruction of its risk by formal we have a on destruction model that looks like that so the 2 slides the 1st flights is just the our interface on that we have a couple of signals from this risk by formal on interface that we read like the instruction but and that the executing the program counter value found this instruction the register values you that on and then we have a couple of of signals that are generated by our specification that the output of this specification of like which register are rich registers should you read Richard registers to do right what values should be right to that register stuff like that on the left the interface of the same forward instructions
arm and then we have a body that looks more like like that all the instructions that just the code the instructions checks if this is actually the instruction the check is for in this case it's an at immediate instructions on and then you have things like of the blind to the bottom about the above 2 fold assignments assigned spec PC right the for examples as OK the next PC must be 5 of 4 bytes and later than the PC for this instruction but we must increment the program counter by value 0 for and executes instructions and things like that yeah yeah so you might see
there is no s such you don't no assertions because this is just the model of what kind of behavior we would expect and then there is a wrapper that instantiates this instance is the based approved and they are the assassins of the main reason money don't have assertions here but is that the output the desired behavior here is because I can also generate monitor cost that can run alongside your car and checked simulation line immolation FPGA if your course doing the right thing but that can be very very helpful if we have a situation where you run on your call fault maybe day is and then you do have some some observable behavior that's not right but maybe there are thousands even millions like he's between the point there can of staff that something is wrong and the point that the process engine thought that divergent from what the specification of sense and if you can I use a monitor choir like that and it's much easier to find books like this the
I a cases some examples of those consistency checks this is actually not complete on and it's a virus a little bit from processor-to-processor what kind of consistency checks you can actually run of with the process of they're looking at on there is a of check if the program counter for 1 instruction so I haven't such that says this is the program counterfeit instruction and is the pro and con for the next instruction and then we can look at the next instruction and you can see is that the program counter for that instruction exited the broke the next program counter value for the previous instruction and they must link together like the on but the poor my our retire instructions all before so it might be that we see the 1st structure faster than the 2nd instruction later but all the possible that it is his the 2nd instruction 1st and then the 1st instruction a later and because of that there are 2 different objects 1 4 and pay in the number of lost and for a pair of instruction the reversible but there was 1 check that checks if the register value reads and writes a consistent and there's 1 check that sees i if the processes and life so then I our idea the processes have found as a constraints that are the memory will always return on our memory regions outnumber ficus things like that that I can use this to prove that the process will adjust suddenly freeze this is very important and this would also proved that the process was not skipping instruction in that says which is very important because some of the other objects actually depends on the process of behaving in this way found and and so forth so that copper of this consistency checks and is a nice exercise due to sit down and a group of people and go through the list of of consistency checks and see which which set of them actually is meaningful order of its set of them actually leaves and an interesting verification gap and you still need to to at checks for this event processing it is a what kind of box couldn't find
and that is so but question because a but it's really hard to give a complete list on it can definitely find incorrect CD thread the inspectors semantic safer just implemented a instruction incorrectly in your court and then this will find it on no questionable are we can find a lot of parks and things like saying unfolding in pipeline interlocks things like that on the things that very real or other stuff in the way you shouldn't you other than on a freezes if you have the slightest check on some box slated to memory interfaces and mold consistency and things like that but that depends on the on things like the size of your cache lines are if this is a feasible proof on the box that we can find that the 1st by former arm things that are not yet covered with the risk platform the uh like the floating-point stuff was his hours but is all of the to do list actively looking on under and a year from now all this this stuff and we included on anything related to concurrency between multiple on our so far my excuse for that was that the risk 5 memory model is not completely specified yet also I would love to actually know what you want to check exactly but right now there is 5 memory model is in the process of being finalized for and have this excuse for much much more so the process is currently
support about peak graph are which is my own processes are then risk 5 record which is probably like the most famous risk 5 implementation and next with 5 on and also a couple of others but they are not part of the year like open source release of the 1st 5 of form so if you would like to add
support for risk 2 with 5 homophily or 5 process than just check out the risk by from repository look at the course directly CV just supported causes like most closely to the quot that you actually have and then just copy that directory and make a couple of small modifications on
so in a few minutes left to talk about things like the ones in that box is another abstractions on the title of this slide could just be abstractions that could cut points in black box is just the 1st day idea behind abstraction and formal methods is that I switch out part of my this time with a different parts with different so accurate that is of course are less constrained and includes the behavior of the original 2nd but might do other stuff as well so the textbook example would be I haven't assigned with counter and I usually the countable just incremental steps of 1 but now I create an abstraction that can skip numbers and it's just the incremental i in our is strictly increasing steps on and this of course includes the behavior of originally design slave I can prove a property with this abstraction and place instead of the just increment by 1 count them that have proven even a stronger property and that includes the same property for the thing with the of the original design on and actually do idea of abstractions by experiment with respect so the main reason why would because it leads up to 2
EC approves on so for example consider that instruction checker that just checks if the core implements the end instruction correct on this for this check go we don't actually the register file that's working we could replace the register file by something that just ignores all right to it on and then ever read something from the register file Johnson arbitrary value that would still include the behavior of a core a function the register file but because the instruction checkables not care about consistency between register-file rights and register file reads on we can still proved that the instruction is implemented corrective arm and therefore we get an easy approved of course we can use this abstraction for Ordos proofs because the other proof that actually check if my register rocks as I would expect it to the on but if the goal through the list of proofs and around all this proves independent then you will see that for each of them it's possible to abstract away a large portion of your process and therefore you you are used and and and an easy approved on depending on what kind of soul was to use some soul was actually a very capable of finding this kind of abstractions themselves so in that case it doesn't really help by adding these abstractions manually but just realizing that the potential for this abstractions down is something that's that's very useful when then guiding our your positions of the split up a large verification problems Asmara verification problems because it would like to split up the problem and the reason that the soul those all the all is capable of of finding useful abstractions that you need to use incentives to prove yeah was a bounded check
we also have our idea of our questions of what bounds to the use of course larger bounds a better but not bonds also you uh you eat something that is harder to compute on and by it ever smaller bounds well then you have approved runs very tricky but maybe you're not very confident that it actually has proven something that's relevant for you so I propose to solutions for this are the fast solution is you can use the same soul was to find traces that covers up events and you could write a list and say I would like to see 1 member read and long memory right and at least 1 ALU instruction executed and things like that and I can ask the so was the shortest race that would actually satisfy and all this stuff on and then that's a trace of say 25 site is then you know OK when I looked at a power that it proved effective I've sighted people I know at least these other cases that are going to become but the more important thing as I usually many other process so you already found on and it's uh it's it's a good idea to do not just fix the box and forget about them but the staff some way of reintroducing the box just to see if your testing the framework works so if you if you have already a couple of packs and all it took me a to find that out of moment to find that the best thing is to just and the black your the sign again and see what other bounds that the necessary for respect formal to actually discover those parts and then you will have some degree of confidence that other similar but would also have been found with the same of bonds so oversights I
have found a box in Britain much every implementation I looked at I found that the box in all 3 processors we found bugs in spite which is the official implementation of risk 5 in C and I found a way to verify murder verified my specifications against spike and in some cases where found the difference within my of specifications by it tunnel all intellectually back in the English language specification and was so because of that found backs and they language preservation was was performed and the future of art
and might advisory support that the floating point is the little list of 64 bit is like half done on we would like to add support for C is ours and and we would like to add support for more cost but this is something that I would like to do is slowly because adding more cores although means you have less flexibility with with changing things on an better integration with free tools because of an armed right now all of that runs with open source tools that I also happen to write also I wrote those tools of that some people actually don't want to my use my open-source tools they would like to use the commercial doors and it's on the 2 Buddhas that I have better integration with those tools but maybe because I don't get licenses to those tools so we will see how the works on yeah that's it our
lives the time for questions the this and in the have so I think about the pressures of 1 of the known theory here we can also and we have 2 questions if temperature questions and we're going to start with microphone number 1 place it the held fixed foot work and we work and the 1st question you told about the risk 5 formal interface this so uh Desmond there
arms ship their final processor with this and interface available 0 yeah that's a great question thank you on this interface has all the output ports and actually when you implement this interface you should not add something to your design that's not needed to generate those output but so what it can do is you can take the version of the core of that interface of the Russian after-call resulted interface then in your synthesis step just remove those output ports and then run a formal equivalent check between that Russian and dear version that you actually deploy on your AC yeah thanks and no 1 should question of how when people see form for malware fication usually others think all if it is refined is excellent so absolutely excellent and uh do you plan to say that it
will find all of their uh Rotem for that process but it depends on what kind of proof you run the most like was with bounded proofs I'm and I you only get a certain degree of confidence are because you only see box that can occur within a certain number of cycles from recent but if you want you can also run a complete proof on there you start with a symbolic state instead of a recent state and then you can say can make sure that you actually check the entire region state space but that's a very very hard thing to do so that's not a melody can project just adding the risk 5 former interface and running some of the tools is probably begin checked at a project if you already have your response processor thank you thank you and we actually do not have time for any more questions and but there will be time after the talk to ask you questions may think yeah but so maybe you
can find me at the Open FPGA which is part of the heart thinking area very great job to put that much information into 30 minutes please help me think live for his wonderful talk you want to watch the
means of the if if if you thank the it
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Titel End-to-end formal ISA verification of RISC-V processors with riscv-formal
Serientitel 34th Chaos Communication Congress
Autor Wolf, Clifford
Lizenz CC-Namensnennung 4.0 International:
Sie dürfen das Werk bzw. den Inhalt zu jedem legalen Zweck nutzen, verändern und in unveränderter oder veränderter Form vervielfältigen, verbreiten und öffentlich zugänglich machen, sofern Sie den Namen des Autors/Rechteinhabers in der von ihm festgelegten Weise nennen.
DOI 10.5446/34941
Herausgeber Chaos Computer Club e.V.
Erscheinungsjahr 2017
Sprache Englisch

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Fachgebiet Informatik
Abstract Formal hardware verification (hardware model checking) can prove that a design has a specified property. Historically only very simple properties in simple designs have been provable this way, but improvements in model checkers over the last decade enable us to prove very complex design properties nowadays. riscv-formal is a framework for formally verifying RISC-V processors directly against a formal ISA specification. In this presentation I will discuss how the complex task of verifying a processor against the ISA specification is broken down into smaller verification problems, and other techniques that I employed to successfully implement riscv-formal.
Schlagwörter Resilience

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