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Reverse engineering FPGAs

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that it the
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and the next talk if being out by Mateus session M. much use is talking about how to reverse engineer FPGA he did it by himself and he will tell you and how he did it and exile the especially reverse-engineered the excelling 7 series and lab ICE 40 theories he knows much more about this than these so please give a warm applause and he is much I the then make but on this that but what is this
Sarg about the this talk I going to explain to you what is the FPGA but how does it work what does it do the what does FPGA stand for and of course I will tell you stories on holidays and shit them show isn't pictures the and so on the what this
talk is about the studies is not about how to use FPGA is I X you cannot use them I never learned very local reached as and so it was not about synthesis i in maybe a quick story why I decided to reverse engineer eyes for the serious 4 years ago the I wanted to build the small CPU and that the problem that chip design and booing chips is far too expensive so the next simpler still solution the what the and after l f FPGA the but they did not want to learn very look the all or vhdl so I decided to go on the the and documents bitstream format and interlayer of anyhow the
FPGA stands for field programmable gate array what means field-programmable the but but in a sense it means that devices in place programmable the so to say it in our life circuit we can just reconfigure the device the gate part is the FPGA simulates implements logic gates the and you're the with a two-dimensional array of logic gates programmable logic gates but I yes but what is logic before I will tell you how and FPGA Warwick's thank the to fall off we have to get down to the the 1 we
have for operators the operators yeah wealth and Northgate's withstand skated with the orig is and was day excuses or gates the on the bottom you can see the truth tables the when we have at the input for example at the OR-gate 0 0 we 0 knowledge boat but let's see what we get 1 and so forth the the that it next thing we can move the but came together logic gates intersection yeah this is
my example also and 1 bit for an edit which is used to implement additional and as you can see it to users to ecstasy or a gates 2 and states but this 1 is free at least August OK that's ever implementations of them the the in on the informal slides the we could see in that we can generate a truth table the Panel when the input states the and what we get on the output the with that we also can combine several logic gates into 1 table the I did the work for the full better if the and
no we have all the inputs with 2 outputs and it's if we for example gets funny 1 on the 0 and we have to care is set to 1 we know the result with be 0 and the carry out will be 1 the the the nice part about this is we don't have to trees from the logic the and we just kind of implemented through logic gates In the lookup table and the look up table is
the smallest part the message this seemed implement the logic gates tha however we need more than 1 look at table of course so the let's assume bits
and the and what you can see here it's a slice indeed 7 0 sightings of the FPGA these are for lookup tables with 6 input speech they all followed by a special care units because implementing edition with lookup tables will take up too many resources and because we needed quite often but it is far cheaper for other manufacturers to include a carry chain the and then the on the output so if it flops the because sometimes we need to synchronize the the States all we need to store 1 bit of information the the we then packed together 1 look up table 1 part of the carriage in and in case of the 7th used to fit Phelps into what's called the logic cell the for logic sentence make up 1 slice but and
2 slices our in group together
the combined with a switched books and interconnect into a
tight the as you can see in we surrounding
dies the and that's all we
implement logic and that's how we're wired the logic tha
the the the now we assume out at that more the here we can see that several of
those ties are grouped together in 2 columns and was not a bit more 1
column with the settings used contains 50 trials and 1 truck that in the middle the this is a rather small the wise it only has 1 100 18th 6 columns which it 1st to 9 falls of 300 ties the the common center grouped
together into regions this particular device has 6 system the and yet the
that's the basic FPGA fabric but we're still missing something we still can't communicate with altered word of the chip for something you for it we need something like a bridge or input output models the so at the borders we have the male trials yeah but are demo and those 2 pi sites the the of course sometimes logic is not enough maybe we need to memory but of course it could implement the memory logic but that's expensive to mentors gave us small units could program yeah article columns but
Block RAM in that particular device the on it's small rectangle contains 36 kilobits of memory of the and there are 100 yeah blocks of RAM and this device some tends memories although not enough the sometimes we need processing power but the implementing error make functions like modification would also use of lots and lots of resources lots of lots of logic so was gave us give the titles the is
being sense thought Digital Signal Processors the or in that case it's just the small addition units combined with the multiplication unit OK now we really know about the basic make up off FPGA but how do we consider it all the speech leucoptera Knowles its values harder dutifully fields known the initial state and how is everything relative for that the with the
bit string the problem of the bitstream is it is undocumented yeah and it's confused which books the terrace provides the initial states this thing is desired switch switch to turn off and on the the goal of revulsion that reverse-engineering FPGA but scanning the bitstream document as the I have 4 years ago I rules ingenuity eyes 40 pj of quick summary the the the
eyes faulty FPGA this is a very very small 1 is optimized for low power consumption the it only has between 384 and so falls of 600 T look up tables of only 4 inputs to in that block RAM lots of small but this very beginner friendly and it's the cheapest form of to the this is the picture the manufacturer gives us but it
shows that the program logic blocks contain fun and contain 8 lookup tables and that the whole fabric is surrounded with the O ties the but we don't know anything about interconnected the and we don't even know how many trials on the new rules non-occurrence there up of but it I but a closer look at the
control of logic block corridor in that case the logic cell the we can see in there is only 1 flip-flop the and it can be bypassed you can use both the Pew output after look table and the 5th they will only for inputs what's special about the rotting in the but these there other the direction
the so you have more than 1 source at each wire the you can do is you put in the right or wrong configuration concert circuits in the devices another thing they provide us with 5 8 over here all the singers they got to every single file and every time and we can choose out those states for the D. N. interconnect between the tides the mainly consists of wires that span a world for plants and what 12 times horizontally and vertically the and of course everything in its tireless collectors its 8 surrounding neighbors that said what challenges with reverse-engineering the eyes 40 FPGA the well we had no knowledge about internal layout the I have no schematic the I had no idea all howmany many wires that where the way to go words which books are all the switch boxes connect to the control logic blocks and even the bitstream won't Coleman's the commanding the FPGA to loads to court bitstream where only partially document as and I change of course is mapping the entire location to the bitmap coordinates but I will show you more details of that later so how the reverse engineered EI eyes for the FPGA the well the
I took a look at took a closer look at the towards the end of gave me the especially in the bitstream generator the the bitstream generators seem to contain 7 the strings the which related to the names to wiring and you kept comparing the big names but the the were behind the D looks like that I could not reach because they commented out of a compiler didn't optimise adults that's why it was easy for me the book amendments undergoes a shitty as faulty FPGA because only had to replace 1 singing jump instruction in the vendor to work the and was able to get everything you name of everything he bit the walls and a short description of its functions but array the that not a funny story about holidays tools written when it tried to the compiler it and look through some functions in its if you could see a where a copy pasted everything together the if if 1 function and it's a combination of print ads and C L 2 you know they need copy and paste that should together another thing I noticed the bitstream containing done and Sears see or cited agreed on citric the but there was not a singing it up close that related to dysfunctional namely ecstasy for old battery Apollon if you implement the psyche regions a check In nominee exotic the the but part of me so I just randomly stop the bitstream generator and took a look at the memory dump and out they generate that that bitstream in ASCII the so at some point and I found that shy and string of ones and zeros in asking and they generate the best part only for the C or C of the I don't know what happened in the program i'd don't want to know what led to distribute these decisions but if the and with p citing 7 serious I arose engineered or partially religion designing services 3 years ago
the I had another challenge because deciding fuse the the 2nd serious it is really really hyper high-performance device the war on the singing it looks a 6 leucoptera of the use upper half the memory of 1 the see the ties in the eyes 40 and even the smallest 7 Sears FPGA as look of table is that the father hence bigger than the eyes faulty ones can and the biggest 1 that has more than 1 . 2 million lookup tables this needs to around 150 thousand titles the the yeah the other resources in the 7 serious the container and the block on
the block has 36 kilobits of data as I mentioned before with the central plot line that is because the altered by way of this is just the bottommost part of the zinc 7 to 20 later I was anymore on knowledge that a model to sing 70 20
this is the particular was I decided to as junior because the containment of tool arm Caltech's 89 % costs that could reprogram the FPGA at the interface with it but I really really like the fault about combining the that FPGA With the interconnect with 50 memory system office processor cores and use that but but then again I didn't want to learn the log of each daily the so I decided through as engineered the which descends serious I mean a to state up mental operations because for example as mentioned before landfalls of France which boxes the if switched books contains the 216 in more to plexus In this 3 thousand 738 possible connection states that's a lot they also connect through 145 wires to neighboring tides and all 117 wires from neighboring ties to them the whole operations suddenly else Mary big the and of course the whole device contains more than 3 million wires and their authority to median of modern 1st 2 million configurations bits which the each of them I had to find out what they do what were the challenges with designed serious yet
the complex design but with this 1 I was not able to to get any debugging information whatsoever the or that through a chain was much more complex than the letters 1 it was something that was written in china so no decompiling there for me I am only as the assemblies because programmer then it was written much nicer the another thing that bothered me I would show you is that there is a small part where the pattern of the pick Buchanan's extract of 2 bit doesn't match the rest the and this part is isolated from love for the error correction part the us all the models with small challenge was mapping the thai locations to the bitmap continents the lower would show you this as a very small section off the bitmap I you can I can generate of the bitstream
the the I can't the when I 1st looked at this else like slack the this
thing seemed like an insurmountable Walter me but already it and you already can see some patterns in there with for example can see that there are some the tanks most probabilities are d configuration data followed look table nice now we only have to find out what the other columns that look like noise steer Of course therefore the switch boxes but mapping them to D to single wireless I was hard yeah the and about mapping the ties to the bit-mapped I another picture the we
can see the the 64 pixels matched to 1 time can arguments this parts or get
this part the maps to you other parts the the the
with the middle part I was puzzled the of course of and these small regular flock of pixels we can see here and here and here the the at the half at to do so how to to and the had to be used for D clock interconnect with beer in the middle we can see there's the
clock but we know that 21st trials on 1 side and 25 times on other side but that's all I got 1st to work with
about the L collecting called that we consider that thing the while the challenge a but I had an idea I rule to small parser that counted the number of bits that were set in each role if this number below us 1 I store the information about 2 years middle part who the out of that I was able to find out the signals using having called or singular collection during error detection extended hamming codes I would love to show you more but it's right below I had a problem with my disk and mental to book and that's kind of where my talk is early and sustained
that this the what can it tell you more about the reverse engineer with 7 serious with the other to a chain we get the necklace we get there in time schematic the and you can extract it no program at all automatic you get information on the tight coordinates you get the names of 2 wires but we don't get the information in the bitstream the but with the knowledge of where the tied states in the bitstream the we can correlate that data to I created several ultimate toward Florida I would have laughed to show them to you the but something went terribly wrong yeah I'm sorry so what are the implications of our work at it's there the because I
a can create an atlas of the bitstream the I am tool cross-compiler bitstreams different architectures with that we can copy extracted reverse-engineer IP costs that our Our otherwise the impenetrable another possibility and is starting project I saw another project I Some with Schiffer together to create and 2nd the target for this open source to a change but and very sorry that my talk got discharge there any questions to
mn thank you and this was it's not the so if you have questions from ITS please come to the microphones the years 1 3 and 4 and to have we have that we can take questions from the IRC chat are wired to that as well and here we have a question here at microphone 1 rule is a rule with you well you pressure what happened to your left what happened we will something about EX thoughts and make and on planning it archaic and hand my windows would try to repair this just freezes like at its heart and happened like 1 long before the whole thing started uh my 2nd question um have you worked on nite links US Patent 6 series no I never cared about the spot once in a what the 6 serious I only want to say throughout his centuries because of the cortical processes in it what thank you thank you and microphone to please things for a book about can you comment on this like middle point of the PGA because you have like this like on there and this idea of white part there is like the error correction codes for half of the FPGA and the other half of the FPGA or how does that work exactly with having cold you normally makes the parity bits into the data of but of course the sightings doesn't want that so they put in the middle and the certain bits that they are already having cold for 1 row I can show you later details when I get them out of my hard-disk there thereof everything think in the thirties with more details thanks thank you might from 3 please I was somewhat puzzled by your remarks regarding your inability to compile the job of suturing you mentioned earlier because usually see missile bytecodes and Chadian is the easiest prey in that regard how come that might be styles come at it from a different direction because I told everything tumor cells I had no idea how to take a child With these letters were trained I created tool 2 words for dead code elimination 1 for example patched everything is jump instruction in the binary so they could get the program flow and I wanna replaced everything calls breakpoint I invoked the Structured Exception handling for from Windows and replaced every opcodes as was executed the in that way I could really use both by 2 ferrets which was easy to comply with as that which I'll I had no idea all detected that results of automated software for that give a love again I never use I always rolled my own software maybe this or other reasons the then we have a question from the IRC chat what of architectures through FPGA is used you mentioned on ones but it wasn't the FPGA itself no and has his own views architectures like CPU's they have the building blocks like the control of logic block the like block speed ties to Yale ties and this young detector then microphone 1 again and I'm I'm wondering whether you have tried to extract some of the device database from divide or some information on our digestive that fossil legal reasons animal I thought of doing that but the binary size thing 1 more and US in size I was like No like it OK I think I am the vital um encrypts action cost so basically you check out in the same way also for XML files which contain some of the device information thing that's quite similar to what I Intel is doing there are those who listen to the in the talk as I have no need for that information because I could get did device information although flight 10 or 20 example projects I just through into the core if you want like interrelated some more details about that we matter fantasies high impressive work thank you and I'm sorry for representation of OK so it's and your presentation we work still impressive um my question was almost the same so you didn't look at GTX or high-speed on my IT cost because it was too complicated I guess all I didn't have a device for that O K yeah OK and I have for all the hardware in my mind a OK thank you I will ask a tedious state of someone make entries do you do any work on talking what did you do any work and talking like bills and the distribution of of the issue the trust I know as long as I have uh some informational multi-column drivers the role drivers follow comes to get OK but you but part which have the i and the 2 is 2 pictures all the schematics where I could zoom in and zoom out but yeah like a patent the microphone to please I am having things let talk and my question is regarding the reprogramming the FPGA fabric from the on context cost to you have a look at that is also possible with the work or it is our but another thing that interests me more the 1st was thinking the 720 and talking about the has to applies that can reprogram the whole thing or partially reprogram it media and of course in reality so the it wouldn't be a problem with that the fledging that of that with the or at the outset made that file wanting about using the zinc is is a combination of this if you have an FPGA parts they are isolated you don't even need to power up the of cheap part but you need to part of the arm part because it's the arm parts that obviously prioritized and that's confuse the 1st extreme OK so I can just use your bitstream and that you generated using your tools I have I have it's a very very very very proved concert place and all tool for small gates and that is with the aisles but it's working and routing and raising the thank you microphone place of what a boat to the timing information that flows to listen to you that I started to extracting the timing information but I want to finish up morals the tide information before I started with that but I have to tools already waiting and that's that would be 1 of text parts of Texas so sometime in the future we can expect to actually use the with the timing analysis and I will talk to because I don't have a really motivation behind that of other than for found is I can't create something great out this interest a community all I would love
to do that but out in all the also becomes to anyone and the microphone to peace so did you get the sum of of the case like the whole thrust scaled boss or ii yet how I did I started with uh started looking at the root of the but before that want to finish up the 7 serious and I don't have a working were too scared and I just want to hold in my hands for the reverse engineer it uh if it you can understand this i'm and the other part of the question that you will get other renders maybe Microsemi all there are might any I 1st considered before I decided to realization as 40 but it a crap and yes I really want to reverse engineer the idea in lectures next because then I a kind of and all the free vandals stupid things thank you and number 1 you have a question concerning the place in rowdy do and what is the basic approach you take to reduce our all the combinations of block placing right now it's just the proof of concept there's no or reducing anything data of course the we use simulated annealing and I really want to get into a what what it called the reduced order of binary decision diagrams OK thank you number 2 please half thank you for the questions that saving I might do we have an tried all to get the bridges between the FPGA and the hot core parts or for example memory aid what makes us from the PGA to the other peripherals in the I started working on that but it's of just reverse at another time I can show you more to that later if you this time thank you and number 3 and how those FEGA applied the bitstream in in what sense now and you put it in the you Art something called as it were hardly there are several the several ways we've using 1 because it does armed prophets process so does more bootloader you can put the whole thing on amnesty cart and it also automatically through the cortex and of course you could use traits that they go you can connect to external STI device for many possibilities great things and we have the question microphone for hi thank you for your talk on the loop I could request could you but represent the whole presentation in sort of organized session may committee I would love to cool things and number 1 again yes I have a question during your studies d you discover new stuff about a PGA backdoors made by NASA in France and all I hallways to detect them but I found ways to detect that the them a kick out of to tokyo uh about you from time to you about that shortly and uh I wanted to say something else about it's funny these things have you been working with which integrate and FPGA and GPU I think such interim of cybersecurity it is absolutely not a good idea to me in the century and FPGA and CPU because uh vernacular like in this state can easily through some few bytes of Cardiff Loading cannot and I will tell you later about that because I had and working on a proof of concept for approval blunt input device OK of united to talk about that this data thank you we have a question in the eyes the jet what is selecting to get a free and open-source FPGA toolchain like with West on for the IC 40 serious what do you mean the place and role to with the eyes faulty I gave the from the findings and T. together with some other guys they create that's the place and all tool but just provide the most information about it with documentation basically I hope that answers that question microphone to please yes thanks he said that you don't do very lucky and BHT so what do you use as input for your design tools the example project of 2 us then I drink on the dates to get some different see and rotting and was sightings you have blocked decided to talk I also have to be my out of presentation OK things number 1 again please hello and between signings forces you to use the XI Forbus between the programmable logic and so on course did you figure out if there's another way to connect these parts what do you mean they don't want me to use the uh bus there's also you are at you all also have like 60 40 Oh yes to get outside the device model between the army drawing and the fabric of K that thank you if you want to can show you what it it's a later I think it will be in this session later the higher ahead and microphone to please could you explain your way of reverse engineering the GATT if you create a bitstream and observe its behavior of the to just created bitstream I have run it I never on the instantly created I only warns of a try a small bitstream I created by myself and that does it so what did you do if you did not grant the bitstreams I just got the knowledge of it I tried to retreat to saying that this information that I got all of to retain only by looking at the bitstream thank you and microphone to again I can talk about the the normal ejectiles like the POL tiles I'll tiles is that some of the different from reverse-engineering the logic styles said yes you get the way you get of information in this almost no external automated you have to look at or I have to look at schematic information who what internal switches are used where to go then I have to create another image where this which is not to use them I can take the difference between the Titan that OK 1 the do you do when there's provide some sort of the methods of the PLO Walter is that yes we want to find information with sightings you know almost everything about the lies good thanks and another question in the area see Chapter when and where would the latest session take place when and where do you want it to take place I I'm not that good with toaccess you've noticed I am more of a conversation guy so maybe you always come to the front after this talk and you can figure out a place to gather maybe at a bar and if there's some free space it's a could big space actually and any more questions it doesn't seem like that so give a water blasting yes that few she was just was you
and in the and I and the world each and the fact
that at
Field programmable gate array
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Metadaten

Formale Metadaten

Titel Reverse engineering FPGAs
Untertitel Dissecting FPGAs from bottom up, extracting schematics and documenting bitstream formats
Serientitel 34th Chaos Communication Congress
Autor Lasser, Mathias
Lizenz CC-Namensnennung 4.0 International:
Sie dürfen das Werk bzw. den Inhalt zu jedem legalen Zweck nutzen, verändern und in unveränderter oder veränderter Form vervielfältigen, verbreiten und öffentlich zugänglich machen, sofern Sie den Namen des Autors/Rechteinhabers in der von ihm festgelegten Weise nennen.
DOI 10.5446/34899
Herausgeber Chaos Computer Club e.V.
Erscheinungsjahr 2017
Sprache Englisch

Inhaltliche Metadaten

Fachgebiet Informatik
Abstract In this talk I describe the basic makeup of FPGAs and how I reverse engineered the Xilinx 7 Series and Lattice iCE40 Series together with the implications.
Schlagwörter Hardware & Making

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