Hello everyone, my name is Matej Simiński, also known as Orson, and I'm here today to tell you about my recent work on extending VHDL support in IKAROS VeryLog.

IKAROS is a free hardware description language simulator. It has been started a long time ago by Steven Williams, who is still its lead developer. It has originated as a VeryLog simulator, and as such has really well covered the language.

There is also ongoing work on bringing system VeryLog, and you can expect the basic syntax to be handled. And now we are trying also to complete the list with VHDL support. Now, many of you have just seen the presentation of Tristan, and may wonder why do

we even bother to bring VHDL support to IKAROS, when there is such a good free simulator. And the answer is, you have a number of good free simulators that handle a single language, but when it comes to mixed language simulators, I

don't know any free solution, and proprietary tools offer that, so I don't see a good reason why we can't have it in our free world. And before we start talking about extending the software, a brief introduction might be helpful.

IKAROS consists of a few smaller programs, and let's say we would like to simulate an adder written in VHDL, together with a test bench given in system VeryLog or VeryLog. To do so, we issue a comment, like the one on the top of the screen.

iVeryLog is the entry point. It's a convenient tool that handles input parameters and configuration files, and also passes data between further stages of processing. The next step is IVLPP, which stands for IKAROS VeryLog Preprocessor.

It's quite simple, it has two main tasks. First one is to unlock macros, and the second task is to detect VHDL files, which are passed further to VHDLPP, which as you can guess is VHDL Preprocessor. That's the main area for development for me, and basically you can say that it translates VHDL to system VeryLog code.

Once you have all the files processed, we move on to IVL, which is the system VeryLog and VeryLog compiler. That's the part where the major processing goes on.

Every input data, which is currently a single stream of bytes, the data goes through parser, a write, a operator, optimizer, and end up in code generator. With a selected plugin, you can determine the output format.

And from the ones delivered with IKAROS, the most interesting one is VVP, which is a text format for IKAROS simulator. Once you have the file, you can actually run the simulation. It's a separate step

from the processing, so you can rerun your simulation many times without repeating the steps. And once you run the simulation, you can get the output that you asked for. For example, text messages or verification of assets, waveform file output.

And you can also hook some C code if you want to interact with the simulated design through the VPI interface that Tristan described very well. That way, you can check the values of signals or interact with them, modify their values.

I've seen big app walls for command-line tools, but if someone wants to use a graphical user interface, there is one noteworthy application for the VPI. It's called IKAROS V-Log Interactive, and it's a desktop development environment based on Eclipse with, for example, integrated waveform viewer.

And I'm pretty sure it also works with VHDL, so if for some reason you don't like command-line, I think that might be the solution for you. Here's an example of VHDL PPP processing. On the left side, you can

see human written VHDL code that is translated to its system very low counterpart. You can see it's a bit chaotic on the right side. Every name is escaped. You have spaces in strange places.

And here, it's a valid, very low code that you can run in any simulator, but there is a reason why we call VHDL PPP a preprocessor and not a translator. Translating between harder languages sometimes might be very tricky, even though they are, you know, in the end, you can do almost everything in both of them.

But there are things that are not directly translatable between them, so sometimes I need to use tricks that are specific to IKAROS and usually just a function written in C using VPI.

That's why it's preprocessor. It just prepares files for the further stage of processing. Now, when we know how does it work, there are just three basic steps to implement a missing feature in the VHDL front-end.

We need to describe rules for parsing, so we need to know how does the expression look like in the input data. Then we need to define functions for elaboration, so we need to give it some meaning. We need to know how to instantiate it for at least basic checks. And then the emit part, so we need to find the system relog counterpart.

And sometimes that might be very tricky, it's just the case that I mentioned that sometimes you need to use VPI for completing the task.

Now, where are we? Currently, you can use quite basic syntax of VHDL. So, if you have a simple file, there is a high chance that you can use IKAROS verilog to run your VHDL design with a test mesh, for example, in system verilog.

Here's a list that for sure is not a complete list of what you can find inside. I just wanted to give you an idea what should be possible right now. And just for comparison, every feature that we add to either system verilog, verilog or VHDL part is backed up with a test to avoid regressions.

And we have over 2K tests for verilog and system verilog and only 80 for VHDL. Also, you should know that verilog and system verilog are probably a bit more complex, but anyway, just the beginning of the work. And just recently I started wondering if what I was doing for the past few months is not a kind of duplication of the work that was put into VHDL.

So, maybe there's another solution for the problem. Maybe we could just combine the two simulators to take the best parts of them.

So, like you can see here, VHDL files go through VHDL, they are processed. And like it's the current case with VHDL, you get object files or you can get VM intermediate representation code. And we need to do the same for Icarus verilog.

So, yeah, all the files go through Icarus and instead of getting the VDP output, the text format, you could also get object files and just link them together with a common runtime library. That could be, for example, JHDL runtime or maybe something else.

Then we could run it as an executable and get results. I started discussing the idea with Tristan and he came up with probably easier solution to the problem. Here we have a main driver that takes all the files, then distributes them to JHDL or Icarus verilog, runs them in parallel,

conveys messages between them using an interface like maybe VPI as it's available, at least partially, in both of the simulators. And yeah, for every simulation cycle you would have to update the status of devices.

And in that way you could get simulation results. This and the previous slide is just an idea, there is no proof of concept for that, but currently I'm exploring the possibilities. So, yeah, I'm going to test it because I think that might be the ultimate solution to our problem with mixed language simulator.

And I hope that Icarus got a bit of your attention, as every free software project we have a very small group of developers and every help is very welcome.

People are very friendly there, you can see there is active development going on. And if you need some more extra information, there are official links that you can get more. Thank you.