Libre-SOC aims to develop a design for a hybrid CPU-GPU-VPU core for a family of System-on-Chip products, from embedded applications, routers, cell phones and laptops, all the way to high performance computing, using proposed scalable vector extensions for the tried and true POWER instruction set. Being a fully documented and transparent design is a core value of the project, ensuring mainline kernel integration with no effort wasted on reversing-engineering proprietary designs covered by NDA (non-disclosure-agreements), while avoiding untrusted binary blobs. The products should “just work”, at its maximum performance and feature set, with full involvement and support for the community. Last year, Libre-SOC labored to produce its first silicon, a test chip, and produced its first Linux-capable networked proof of concept on an FPGA (field programmable gate array) development board. Using a completely FLOSS toolchain, any developer can build and test this design on their own computer, run it in hardware in a supported FPGA development board, or even build a full ASIC chip layout. In this talk I’ll present topics of the ongoing architecture design and formal testing, being written in a modern, developer-friendly, Python-based hardware description language.