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00:00
Chatten <Kommunikation>EchtzeitsystemVideokonferenzZählenTeilmengeRechter WinkelStabRekursive FunktionBefehlscodep-BlockProgrammierungBus <Informatik>BitSoftware EngineeringBildschirmfensterIterationInverser LimesMedianwertSupercomputerImplementierungFormation <Mathematik>MaschinenspracheZahlenbereichRechenwerkDokumentenserverMereologieKombinatorLoopGenerator <Informatik>SimulationKontinuierliche IntegrationSoftwareentwicklerAdressierungEinfache GenauigkeitSkriptspracheCodeSoftwaretestDivergente ReiheMAPInstallation <Informatik>DivisionProgrammiergerätKonditionszahlMultiplikationsoperatorProfil <Aerodynamik>Element <Gruppentheorie>Flip-FlopInformatikEin-AusgabeHardwareVerzweigendes ProgrammFlächeninhaltSchreiben <Datenverarbeitung>AdressraumDatenfeldInterface <Schaltung>Lesen <Datenverarbeitung>SuchmaschineFunktion <Mathematik>HalbleiterspeicherSchreib-Lese-KopfBildschirmmaskeHypermediaLeistung <Physik>Reverse EngineeringCASE <Informatik>ÄhnlichkeitsgeometrieVLSIArithmetisches MittelTabelleGruppenoperationKontrollstrukturDateiformatProgrammverifikationMailing-ListeElektronische PublikationE-MailVerknüpfungsgliedResultanteEinfügungsdämpfungTechnische InformatikDickeBimodulRFIDSynchronisierungInformationOffene MengeParserCodierungWärmeübergangLastWort <Informatik>Zeiger <Informatik>Kette <Mathematik>PseudopotenzialVorzeichen <Mathematik>CoprozessorQuick-SortTelekommunikationDualitätstheorieUmsetzung <Informatik>Twitter <Softwareplattform>ComputerVersionsverwaltungTypentheorieSchnittmengeExogene VariableWellenpaketHybridrechnerComputersimulationHardwarebeschreibungsspracheDreiecksfreier GraphToken-RingParallele SchnittstellePufferüberlaufWeb-SeiteMaßerweiterungField programmable gate arrayKlasse <Mathematik>VariableComputersicherheitPunktspektrumDifferenteZusammenhängender GraphGanze FunktionMinkowski-MetrikParametersystemBootstrap-AggregationBereichsschätzungRemote AccessVirtuelle MaschineUmwandlungsenthalpieNotepad-ComputerInformationsspeicherungDifferenzkernProgrammierspracheQuellcodePhysikalismusSnake <Bildverarbeitung>VollständigkeitProzess <Informatik>KomponententestSoftware Development KitFehlermeldungt-TestMessage-PassingArithmetisch-logische EinheitWasserdampftafelSinusfunktionFunktionalStabilitätstheorie <Logik>WhiteboardIntelCliquenweiteARM <Computerarchitektur>Befehl <Informatik>MakrobefehlStellenringKontextbezogenes SystemFreewareSystem FExt-FunktorTDMANamensraumURLNichtlinearer OperatorPunktSpeicherabzugKonfigurationsraumKonfiguration <Informatik>AnalysisInternetworkingStatisches RAMEinfach zusammenhängender RaumRegulärer Ausdruck <Textverarbeitung>ZweiGamecontrollerEmulationTrigonometrische FunktionComputerspielMixed RealityFigurierte ZahlGeradeSampler <Musikinstrument>OrtsoperatorEmulatorÄquivalenzklasseProgrammschleifeCompilerWurzel <Mathematik>WechselsprungEntscheidungstheorieGanze ZahlEigentliche AbbildungSoundverarbeitungSchlussregelSoftwarePhysikalisches SystemHeegaard-ZerlegungErwartungswertFraktalgeometrieHackerBootenSmartphoneIRIS-TPackprogrammRechenbuchAlgorithmische ProgrammierspracheWeb SiteBesprechung/Interview
00:43
TaskViereckKubischer GraphFreewareSystemprogrammierungARM <Computerarchitektur>GraphikprozessorSystem-on-ChipServerHardwarebeschreibungsspracheCodeTreiber <Programm>Gebäude <Mathematik>FeldrechnerBefehlsprozessorQuellcodeLeistung <Physik>CodeHardwarebeschreibungsspracheComputersimulationComputeranimation
01:39
WhiteboardPhysikalisches SystemCodeField programmable gate arraySimulationProgrammierungDigitalsignalMathematische LogikWeb-SeiteQuellcodeHardwareComputersimulationAnalog-Digital-UmsetzerArithmetisch-logische EinheitFreewareInformationSpeicherabzugHardwareSimulationCASE <Informatik>ProgrammierungMixed RealityHardwarebeschreibungsspracheMaschinensprache
02:39
SinusfunktionInverser Limesp-BlockHierarchische StrukturCompilerSimulationMathematische LogikVLSIMobiles EndgerätRouterQuellcodeSoftwareentwicklerBetafunktionDigitalsignalAnalogieschlussKonfiguration <Informatik>Prozess <Informatik>Shape <Informatik>RandwertFreewareService providerPhysikalismusStabWellenpaketProgrammierungGruppenoperationElektronische PublikationComputeranimation
04:33
AbstraktionsebeneDatenflussFreewareE-FunktionWhiteboardPolareKontrollstrukturSimulationUmkehrung <Mathematik>SDRAMPhysikalisches SystemComputersimulationp-BlockSoftwareentwicklerField programmable gate arrayNebenbedingungDokumentenserverService providerAttributierte GrammatikInverser LimesEin-AusgabeAggregatzustandSystemplattformInformationZählenMereologiePufferüberlaufSynchronisierungParametersystemRechenwerkBimodulOvalInterface <Schaltung>HardwarebeschreibungsspracheCodeKlon <Mathematik>QuellcodeProzess <Informatik>SkriptspracheEigenwertproblemInstallation <Informatik>TopologieSimplexverfahrenSystem-on-ChipWeb-SeiteOpen SourceLeistung <Physik>ImplementierungVersionsverwaltungIntelBefehlsprozessorTaskMailing-ListeTreiber <Programm>MaßerweiterungVerschlingungDichte <Stochastik>Element <Gruppentheorie>Offene MengeSyntaktische AnalyseDateiformatBildschirmmaskeSoftwareZählenDokumentenserverInformationSoftwareentwicklerBefehlscodeCodeMultiplikationsoperatorPufferüberlaufTechnische InformatikSkriptspracheBimodulSynchronisierungInverser LimesVirtuelle MaschineE-MailKlasse <Mathematik>Mailing-ListeSoftware EngineeringEigentliche AbbildungComputeranimation
08:57
TabelleSingulärwertzerlegungTaskLastLie-GruppeMailing-ListeSimplexverfahrenBefehlscodeFreewareE-FunktionGleitkommaprozessorArithmetisch-logische EinheitKonstanteSystem-on-ChipKubischer GraphTeilmengeCodeComputersimulationLeistung <Physik>SoftwaretestROM <Informatik>Architektur <Informatik>BefehlsprozessorPhysikalisches SystemSimulationDatenfeldParserWort <Informatik>MakrobefehlLesezeichen <Internet>BildschirmmaskeGarbentheoriePunktWeb-SeiteAdressraumVersionsverwaltungInformationsspeicherungMaximum-Entropie-MethodeFrequenzgangInklusion <Mathematik>MinimumSCI <Informatik>QuellcodeDateiformatIndexberechnungSystemaufrufViereckEmulatorDigitalfilterMAPFormale GrammatikToken-RingSpannweite <Stochastik>Prozess <Informatik>p-BlockRegulärer Ausdruck <Textverarbeitung>Funktion <Mathematik>Poisson-KlammerZählenSpezielle unitäre GruppeDefaultBefehl <Informatik>Nabel <Mathematik>VerzeichnisdienstDatensichtgerätBildschirmmaskeRechter WinkelQuellcodeInformationsspeicherungSnake <Bildverarbeitung>FehlermeldungBitMessage-PassingInternetworkingGeradeImplementierungProgrammierspracheTypentheorieDatenfeldAnalytische FortsetzungParserTeilmengeUmwandlungsenthalpieVirtuelle MaschineWikiProgrammierungSoftware EngineeringDateiformatToken-RingNichtlinearer OperatorEinfach zusammenhängender RaumWeb-SeiteSoftwaretestZahlenbereichCodeRechenwerkMereologieBefehlscodeLastComputeranimation
15:42
KontrollstrukturWort <Informatik>DatensichtgerätLesezeichen <Internet>MakrobefehlPhysikalisches SystemDatenfeldSimulationParserElektronischer FingerabdruckProgrammSpannweite <Stochastik>HochdruckQuellcodeDateiformatIndexberechnungMini-DiscSpezielle unitäre GruppeCachingInnerer PunktKernel <Informatik>SystemzusammenbruchAdressraumVersionsverwaltungInformationsspeicherungDisk-ArrayMaßerweiterungStichprobeMereologieBimodulFunktion <Mathematik>MAPEin-AusgabeVererbungshierarchieDefaultMathematische LogikKreisbogenSystemplattformRestklasseBildschirmmaskeVariableÜbertragAdressraumHardwarebeschreibungsspracheLeistung <Physik>KonditionszahlVerzweigendes ProgrammProfil <Aerodynamik>Vorzeichen <Mathematik>DivisionHalbleiterspeicherComputersimulationMaßerweiterungBefehl <Informatik>ÄhnlichkeitsgeometrieCompilerVariableProgrammierungLesen <Datenverarbeitung>ZahlenbereichInterface <Schaltung>Funktion <Mathematik>Nichtlinearer OperatorDatenfeldDateiformatLastSchreiben <Datenverarbeitung>Kontextbezogenes SystemStellenringHackerTypentheorieFunktionalAdressierungNamensraumVirtuelle MaschineRechenwerkZweiVersionsverwaltungImplementierungParametersystemBootstrap-AggregationSimulationBereichsschätzungParserPunktComputeranimation
22:27
Arithmetisch-logische EinheitComputersicherheitFreewareKonstanteBefehlscodeTabelleLastSingulärwertzerlegungLogik höherer StufeArchitektur <Informatik>Gerichtete MengeBildschirmsymbolOperations ResearchBefehl <Informatik>CASE <Informatik>Inverter <Schaltung>DefaultLesezeichen <Internet>MakrobefehlDatensichtgerätÜbertragFunktion <Mathematik>MaßerweiterungCodeDatenfeldInnerer PunktSimulationParserMAPDampfdruckROM <Informatik>KonfigurationsraumParametersystemGruppenoperationInterface <Schaltung>SpeicherabzugPell-Gleichungp-BlockHochdruckGamecontrollerProxy ServerMIDI <Musikelektronik>BildschirmmaskeInformationVerzeichnisdienstWort <Informatik>FehlermeldungCloud ComputingChi-Quadrat-VerteilungSchaltwerkVersionsverwaltungVorzeichen <Mathematik>Codierung <Programmierung>SchieberegisterCliquenweiteAdressraumWurm <Informatik>SISPSoftware RadioATMTelnetTreiber <Programm>DebuggingOffene MengeMagnetbandlaufwerkIdeal <Mathematik>DigitalsignalMereologieKonfiguration <Informatik>OISCRuhmasseSchlussregelProgrammierungBefehl <Informatik>Konfiguration <Informatik>Funktion <Mathematik>SpeicherabzugUmsetzung <Informatik>UmwandlungsenthalpieKonfigurationsraumHardwarebeschreibungsspracheStabInterface <Schaltung>Regulärer Ausdruck <Textverarbeitung>HardwareElektronische PublikationInterrupt <Informatik>CliquenweiteCodeGamecontrollerField programmable gate arraySchaltwerkÜbertragBitZahlenbereichCASE <Informatik>Nichtlinearer OperatorMereologieData MiningLesen <Datenverarbeitung>Ganze ZahlPufferüberlaufÄquivalenzklasseKonditionszahlExt-FunktorVorzeichen <Mathematik>FunktionalRechenbuchDickeComputeranimation
28:42
App <Programm>MereologieSchaltwerkInformationOffene MengeSISPTreiber <Programm>TelnetKonfiguration <Informatik>Single Sign-OnSpeicherabzugSimulationLokales MinimumAdressraumBinärdatenSechseckSoftwareKontrollstrukturTorusRohdatenBootenSerielle SchnittstelleProgrammNP-hartes ProblemFirmwareTermCachingFormation <Mathematik>DatenfeldParserMaskierung <Informatik>Elektronische PublikationFehlermeldungInterface <Schaltung>MagnetbandlaufwerkInklusion <Mathematik>Funktion <Mathematik>Mailing-ListeKreisbogenMultitaskingDatensichtgerätLesezeichen <Internet>MakrobefehlSynchronisierungCliquenweiteSystemplattformBimodulUmsetzung <Informatik>DefaultStereometrieMenütechnikPlastikkarteCase-ModdingHill-DifferentialgleichungWeb-SeiteMAPGlobale OptimierungNichtunterscheidbarkeitFaltung <Mathematik>Total <Mathematik>Sukzessive ÜberrelaxationPhysikalisches SystemBimodulFunktion <Mathematik>Ein-AusgabeCliquenweiteRechter WinkelTDMABitStabilitätstheorie <Logik>MereologieVerknüpfungsgliedCompilerDreiecksfreier GraphMAPHardwarebeschreibungsspracheDivergente ReiheComputersimulationProgrammierungZahlenbereichLoopSkriptspracheDatenfeldMultiplikationsoperatorSoftwaretestMedianwertResultanteMaschinenspracheFigurierte ZahlEmulatorInterface <Schaltung>CodeSichtenkonzeptArithmetisch-logische EinheitHardwareKombinatorHeegaard-ZerlegungFlip-FlopComputeranimation
34:41
Lokales MinimumKreisflächeGravitationsgesetzSigma-AlgebraTaskLesezeichen <Internet>Zusammenhängender GraphRechter Winkelp-BlockProgrammierungRoutingProgrammverifikationURLComputeranimation
35:43
InformationBefehlsprozessorHash-AlgorithmusCase-ModdingAtomarität <Informatik>Token-RingHyperbelfunktionTelnetDatensichtgerätMakrobefehlLesezeichen <Internet>SpeicherabzugPhysikalisches SystemSkriptspracheFehlermeldungElektronische PublikationInterface <Schaltung>KreisbogenTreiber <Programm>TeilmengeArchitektur <Informatik>MAPE-MailBildschirmfensterDefaultSimulationEinfache GenauigkeitReverse EngineeringDampfdruckIterationInnerer PunktIndexberechnungSinguläres IntegralTeilmengeMereologieComputeranimation
36:22
App <Programm>SoftwaretestFreewareKubischer GraphVersionsverwaltungBrowserExplorative DatenanalyseProgrammierumgebungQuellcodeSimulationVarietät <Mathematik>HardwarebeschreibungsspracheWeb-SeiteCase-ModdingSpeicherabzugInterface <Schaltung>TelnetMakrobefehlDatensichtgerätLesezeichen <Internet>FehlermeldungInformationTeilmengeKreisbogenAppletArchitektur <Informatik>Treiber <Programm>OISCDateiformatBinärdatenROM <Informatik>LastAdressraumEin-AusgabeFunktion <Mathematik>Bitmap-GraphikE-FunktionVerschiebungsoperatorComputersimulationSimulationCodeSchreiben <Datenverarbeitung>AdressraumHalbleiterspeicherMultiplikationsoperatorResultanteSoftwaretestLesen <Datenverarbeitung>ComputeranimationProgramm/Quellcode
37:53
Wurzel <Mathematik>Mailing-ListeJensen-MaßBetafunktionSpannweite <Stochastik>GruppenoperationSoftwareSinguläres IntegralWeb-SeiteTrigonometrische FunktionElektronische PublikationDistributivgesetzKonditionszahlArithmetischer AusdruckService providerFitnessfunktionEreignishorizontMathematikKubischer GraphFreewareLokales NetzCliquenweiteProgrammschemaPermutationUmkehrung <Mathematik>IndexberechnungFunktion <Mathematik>TOEBinärdatenProgrammschleifeE-FunktionTaskIdeal <Mathematik>RobotikKryptologieRouterVideokonferenzFormale GrammatikLeistung <Physik>SoftwaretestTrigonometrische FunktionCodeImplementierungLoopIterationGenerator <Informatik>Rekursive FunktionVersionsverwaltungFlächeninhaltProgrammschleifeInformatikComputeranimationProgramm/Quellcode
39:29
AbstraktionsebeneDatenflussDreiQuellcodeTermFreewareRFIDSystemprogrammRuhmasseSoftwareentwicklerKonstanteBetafunktionKonfiguration <Informatik>Shape <Informatik>Prozess <Informatik>DigitalsignalAnalogieschlussRandwertService providerMAPWeb logInformationFlächeninhaltGarbentheorieSkriptspracheMultiplikationsoperatorAlgorithmische ProgrammierspracheProgrammiergerätWurzel <Mathematik>ComputeranimationVorlesung/Konferenz
40:12
Element <Gruppentheorie>ProgrammierungKontextbezogenes SystemBitOrtsoperatorMAPSchreib-Lese-KopfHardwareBesprechung/Interview
41:50
IkosaederSoftware EngineeringReverse EngineeringFreewareKontrollstrukturQuick-SortMereologieProgrammierungDifferenteHardwareKonditionszahlMailing-ListeE-MailComputerVerknüpfungsgliedFraktalgeometriePunktSchlussregelSoftwareentwicklerSuchmaschineMAPRFIDTwitter <Softwareplattform>Rechter WinkelBetrag <Mathematik>SoftwareBootenTypentheorieUmsetzung <Informatik>ARM <Computerarchitektur>EntscheidungstheorieHardwarebeschreibungsspracheKette <Mathematik>Exogene VariableComputersicherheitCoprozessorUmwandlungsenthalpieVersionsverwaltungQuellcodeWärmeübergangMakrobefehlWellenpaket
Transkript: Englisch(automatisch erzeugt)
00:06
Hello and welcome back. This will be our final talk before our next break, and it is a slightly different setup to the other talks. This talk is being delivered by Luke Layton, who is a Libra ethical technology specialist.
00:24
It is pre-recorded, but Luke himself is present at this conference and available in the chat. So at the very end, we will be having a traditional Q&A, but as the video is playing, he will be available to answer questions in real time.
00:40
Without further ado, let's begin. Hello and welcome to the talk on the LibraSoft project for EuroPython 2021. So we use Python for pretty much everything in here, and I just want to take the opportunity to go over that.
01:00
Now, there's quite a lot to cover, so I'll just apologize in advance. That is going to be very much of an overview, but I just want to give you a glimpse into the different aspects of where we use Python in this project. So the first thing is that it's a Python simulator of the power instruction set,
01:24
which we use for experimentation. It's only about 2,000 instructions a second, but we don't care. It's written in Python, and that's more important for code clarity than anything else. We use Numigen for the HDL. HDL is a hardware definition language.
01:45
Now, this includes a simulator, its own simulator, so it will do gate-level simulations similar to Verilator and other simulation tools for HDL.
02:08
We then compile that using a program called Yosys, which outputs Verilog, which is a more standard language, but we treat it in this case as a machine code target.
02:26
That Verilog is then handed over to Coriolis 2. Coriolis 2 is written in a mixed Python and a mixed C++ and Python.
02:40
It's a VLSI tool, so it's a complete toolchain, so you specify the program and the layout in a Python program, and it will then action that and create right down to the GDS2 files for you, and you can then send those to your foundry and get a chip back. So the other thing is chips for makers have created a cell library,
03:11
which is needed. We'll go over this later on. Chips for makers have created a cell library, specifying it in Python, where you run the Python program to generate the cell libraries
03:26
given what's called the PDK, the physical design kit, for the foundry. Now, in most cases, that's under NDA. However, fortunately, there's a couple out there. One of them is 3PDK45, which is an academic PDK for training students, and there is a recently Skywater
03:45
have released a 130 nanomatter PDK. Normally, you would do this under NDA, because I think so staff himself has to run. He has specified, for example, the TSMC 180-nanometer PDK. He's
04:00
got access to that, so under that NDA, he generates the cell library. He runs the program, which generates the cell library, which is suitable for TSMC 180-nanometer. He can't tell us what that is, but at the high level, we can run a parallel path along the way using the 3PDK45,
04:26
so we can track what we're doing. That's what we did for the 180-nanometer ASIC when working with someone at lib6. Now, so I'd like you to explore Numigen. It's quite
04:42
an absolutely fantastic HDL, very well documented, and there's tutorials online, things where you can see a thing now just briefly here. Here's your module. It has two signals. Here, there's a count, so on each clock sync is a synchronous clock, so on the
05:07
next clock cycle, count will be equal to count plus one, and here, there's an overflow detection, so if it hits a limit, it will set. That's combinatorial, so there's no
05:23
time limit on that. It's always generating a signal, and in here, if that overflow is detected, then on the next clock cycles, the count is set to zero, else it's count plus equals one,
05:43
so here you can see it's just a counter. Now, what's really nice is that we have standard Python classes and modules with the expected behavior of documentation, which of course Sphinx understands and creates what you need, so it's absolutely fantastic
06:01
as far as readability is concerned and expectations. Verilog hardware engineers are not software engineering trained, and it really shows,
06:20
so here's some repositories we've got. I think it is a proper Libra project, so we have this, we have mailing lists and mailing archives, and we also have an IRC channel, etc. So, development is done in real time. It's not done according to the I'll do it when you're, I'll release it when it's ready thing. We are a Libra project.
06:45
So, just to say, if you'd ever like to help us or have a set procedure, we can go through this document on the website. Here's how to get started, and this is much easier
07:01
just by using what we call the DevEng setup scripts, so you can just run those in an automated fashion. For example, here there's that cloning of those repositories, then running, hey look, Python set up what I develop. That's to make sure it's in place, so you can actually edit the code. We don't do Python setup install,
07:24
because you'd be, you need to be able to edit the code in place, and off you go. And likewise, one install the dependencies, I think another script there, so it's all documented and needs to get set up. One for CocoaDB, one for Egress Verilog, etc.
07:47
So, we picked OpenPower, because it's a supercomputing instruction set with 25 years history. So, the end user license agreement is okay, absolutely fine. I had a very nice
08:05
chat with Mendy from the OpenPower Foundation about it, and it's very, very reassuring. The OpenPower Foundation, in most things, has been absolutely fantastic about this project. It's really quite exciting. So, what we did is, as a software engineer,
08:22
you don't do stuff by hand if it can be done automatically. So, what we decided to do was to extract information from the OpenPower specification, and to write machine, put it
08:41
into a machine readable format, and then first write a decoder and a parser, and including this, a simulator. All right, so the first thing we had to do was to decode the major opcodes
09:02
and the minor opcodes into tables, and these are like microcode ops. All right, now these are originally, so you can see that, you know, major opcode 34 is a load store operation, and it's the instruction LPZ. All right, now all of these actually came from
09:28
microWatt, the microWatt source code, which has been a fantastic reference implementation that we used. It's in VHDL, but both Anton Blanchard and the rest of the team are software engineer trained, so they put code commits in and did continuous integration,
09:47
unit tests, and etc, etc. So, we extracted these tables and put them into machine readable CSV files, okay, and then put them behind a wiki. Whilst that's loading, I'll do this one as well. So,
10:12
what we also did was we extracted the pseudocode from the specification, now, and split it down into separate pages. So, for example, I know what's going on,
10:24
my internet connection's gone. That's annoying, but I have to wait for that to come back. Let's go and have a look at the source code here instead. So, here is the markdown files,
10:41
which, this is for the store B instruction, for example. Now, that D form there indicates that it is to be, indicates the layout of the fields. So, here's your specification. Ah, store word, D form. All right. So, there's your pseudocode, which is in the specification. Now,
11:03
the specification actually says this is, we're not supposed to make this, this is not supposed to be executable. We went, nah, forget that. I was saying we're making it executable. So, because, you know, it's correct. You know, we know it's going to be correct. So, that's store B. STW. There's STW for us. There's D form. Now, the D form says that the layout is as follows.
11:27
Okay. In bits 0 to 5, there'll be the number 36, which is the store W. And then, RS is in bits, in fields, bits 6 to 10, RA is in 11 to 15, etc. Now,
11:46
that table, the one I was saying, percent one. Find D form. D form, capital letters. There we go. Right. Here's one of the D forms. So,
12:02
which one was it? D there. Yes, this one. Okay. All right. And this is a machine, we deliberately made it machine readable. The rest of the specification has, let's see, the failed
12:20
find RT, field RT. Yeah. So, again, this is in the specification. This is machine readable. All right. Python program. You can see that that was the D format there. All right. So, the next, here we go. So, the next bit in the puzzle was to actually convert this
13:04
pseudocode into executable Python. All right. And for that, I decided I absolutely love Python ply. All right. So, I recovered the garden snake example, which is a subset of Python,
13:21
and I fixed several of its errors. It, ply is an LALR parser based on yak and flex. Yak, flex, bison. But the actual language itself, Python, doesn't lex properly in a single
13:44
pass. Turns out that you actually have to do some fixing of some of the indentation. So, I
14:01
look for the tokens and add an extra indent, a token, when the opportunity is detected, and didn't indent a tracker. And that way, able to turn it into something that can be properly parsed by an LALR parser. Now, there was also a few other things that needed dealing
14:29
with silent keyword fall through in things. It also skipped some text blank lines. And also, the syntax here, it turns out to be this syntax turns out to be Python like.
14:46
It's not exactly Python. But it's close enough that it was able to adapt the garden snake thing. So, I changed the tokens rather than colon, if test colon. I used if test then.
15:01
And inserted the token. So, that's what this program does. Is it, oh, there we go. If token type equals then, then replace it with a colon. And if it's an else, then we want to yield the else keyword and also add in a colon. Because that makes it a Python syntax.
15:26
Same with do, et cetera, et cetera. All right. Then so, for the next thing, we actually have to have a page reader which reads the syntax of the things and extracts that code. And these forms, this is actually very important part of the part of what we're doing.
15:47
Followed by, finally, an actual parser which if you're familiar with Python ply, you have the BNF back us now format syntax in the comment field. It's a fantastic idea. The latest version of ply actually has it as a decorator which is kind of nicer because
16:04
you can then use the comment field for actual comments. And in this way, we end up with some code. And what was SDW. And we end up with an operation. This is what the compiler outputs.
16:31
All right. So, memory sign, memory sign there, you know, assigns to memory at that address. And so, the, you know, that's get register or zero. Lots of little hacks like
16:45
this, but it calculates the effective address plus sign extension on the immediate. Notice here that the D, the immediate is not actually in here. What we've done is we've done a decorator which injects local variables into the context by actually altering the globals and the locals
17:08
of the function. Yeah, I know. And then on exit, it will extract anything that's been modified. So, in this case, that same function will extract RA from the namespace or any other
17:25
variables that have been modified. So, that's how that operates. And it creates, so, we can write our own simulator now. Let's have a look at one of the
17:52
better. Yes. Okay. So, let's have a look at this one now. So, here we're actually running the simulator, the Python simulator. So, those instructions got decoded
18:09
in Python by machine reading those formats. So, where we have this fields format here,
18:23
sorry, sorry, one second. So, where we have this format here, we match that against the relevant instructions format here. Excuse me. So, then we can pass in some initial memory
18:43
values that we want to do and then run that simulated instruction and assert and compare it against the expected value afterwards. And we do thousands of these tests. Now, to double check this, we weren't confident that we got it right. So, what we did
19:05
was went, well, you know, there's an implementation of power instruction set simulator. It's called QEMU. Why don't we use the machine GDBMI, GDB machine interface to actually connect to QEMU. And here's your arguments for the,
19:28
you know, one running little engine or big engine, no graphics thing and start it up and then upload the program, the exact same compiled program to QEMU and then upload memory.
19:43
All right. So, do the exact same thing and load some initial memory values and run the program and then check the registers afterwards. And then that way, what we can do is we can do co-simulation side by side of QEMU with our simulator, all from Python.
20:05
And then we do the exact same thing with the HDL. So, we're doing this bootstrap process, develop a very slow simulator in Python because it's easier to read and read and understand. Then cross reference and check it against QEMU by
20:24
co-simulating the R simulator versus QEMU. Once we find that that's correct and it can run, we have confidence in R simulator, we go back and run the HDL, the Nametian simulations against the Nametian simulations against the Python-based simulator. All right.
20:49
And, you know, thousands, almost literally thousands of unit tests, just to make absolutely sure that we're confident in what it's doing. Now, let's have a look at the add instruction
21:01
here. Fixed point, load and store, fixed point, move and assist, third point arithmetic instructions. Okay, brilliant. So, here's the add instruction here with add immediate. All right, let's do the... no, not that one.
21:27
Ah, brilliant. Add rt equals ra plus rb. All right, brilliant. Okay. So, we divide it down into separate pipelines. So, let me show you those.
21:48
Function units. So, there's an ALU pipeline branch condition register div unit and these are divided down by the profile register. So, anything that needed a similar number of read
22:02
and write registers would put it in the same pipeline. So, this is Nametian elaborate. Bear in mind, here's your... here's that operation come... let's have a look. Here's your switch statement. Now, it's switching on the instruction type.
22:23
That instruction type comes from the... let's actually search for op add. Oh look, there we go. Op add. There we go. There's all the add operations here. All right. So,
22:41
it says you want to read ra and rb operate operations. Notice, you remember from the specification, it said it needs ra and rb. All right. So, this... so... No, it's back. Brilliant. So, op sop underscore add. Here's our version. That's op immediate.
23:03
So, this is the... this is the csv files which are read by Python. So, that's add ic add integer with carry instruction is that one. Mine are code 31. That's the equivalent of the thing. So, here's the code comment add
23:20
instruction. All right. So, add r8 rb and add destination is rt. And, oh look, it has... it can do condition registers and output. So, switch statement, you know, it's written in Python. It's got comments. So, here's your add. So, what we're doing here is we're actually doing a
23:47
65-bit add which allows us to do the carry. And then the carry overflow is a 32-bit... 64-bit carry. So, that colon minus one, that takes the 65th bit. And there's a calculation
24:07
for the 32-bit carry overflow which came from microWatt. So, sign extend just calls a function and again the switch statement is if the data length is one. So, this is for ext b ext
24:23
half and ext w. The different different instructions. And then we end up joining all those together, those pipelines, etc. I'm going to have to move on quite quickly because we're starting to... I've got quite a lot else to cover. So, now once that's all done,
24:46
we can then output it as Verilog. So, we can generate a core here with different options
25:02
because those options are passed in to the program which, in a config file, it will, in a configuration object, it will... Python, the whole reason why we're using Python is because we can enable at compile time, this is a compiling into Verilog, we can...
25:26
Oh, there we go, there's your options, the specification. We can pass this in and then do if reg width equals equals this or if we want the zix controller interrupt controller to be generated, then output certain stuff into the Verilog thing. So, for the libresoc 180 core
25:49
which went to ASIC, we needed a way to add four SRAMs, four 4K SRAMs, but running the simulations, we didn't want that, so we made it an option here.
26:01
So, there's the Numetian Verilog convert. Now, once that's converted, we can then run it, run a simulation. And this is compiling that up and off it goes. And
26:22
now, one of the other things that you need when developing ASIC is you need a JTAG interface. So, you don't think, you know, you just take it for granted if you've ever done embedded
26:41
computing development, you just take it for granted that there's going to be a JTAG interface. Well, somebody has to implement that. All right. And very kindly, staff from Chips for Makers made a Numetian HDL which implements a fully functioning JTAG TAP interface.
27:04
And we can set the manufacturer ID and then when you put that either into FPGA or ASIC, or in this case in a simulation, which I'll show you in a minute, you can get that manufacturer ID back. But one of the other things,
27:24
one of the things we needed was the ability to upload programs over JTAG. So, because we're using Wishbone interface as the bus, staff added the ability to connect to the Wishbone interface over JTAG. And through this, we're able to actually upload programs even to
27:47
the simulator. Now, I don't know if you're familiar with OpenOCD. It's basically a way to manage hardware. But in this case, what we're doing is we're managing the simulation.
28:01
The simulation, so we've got a JTAG interface operating here and a remote bit banging interface is connected up. So, whilst that is running the BIOS, we've connected over OpenOCD and sent some commands to it. TDI transmitted the data and TDO. It has connected and found,
28:29
oh look, there's a manufacturing ID. Well, hey, there's that ID 018FF, which was a certain part number 0001. So, that's from here. Where is it?
28:50
Part number 001. And if you convert that, you'll find that that was 0x18FF. So, from here, we can write some scripts. And let me see if I can find them.
29:08
And let's debug. Yeah, yeah, vi debug. So, that's a firmware upload. This is a command which if I run this, it will actually upload a program using the same
29:25
test stuff that we did earlier. So, a very simple loop program using the same compiler to generate instructions. We can pass those compiled programs
29:40
over the JTAG interface to the system that we're connecting to, uploading it over Wishbone and remotely controlling it. Now, what's really nice about this is that the exact same program, the JTAG command system, can be used on the simulator and the FPGA
30:04
and the emulator once we extract from the simulator from the VLSI tools and re-simulate the HDL after it's been laid out. And when you come to it, we'll have a series of programs
30:21
that when we get the chip back, we can actually test the things. And it's exactly the same code each and every time. So, we're checking again and again and again and again at every single level that what we're doing actually works. Now, let me leave that one.
30:47
Now, so, here was the simulator which was the Verilog code, which was after it was, let's lubersock.v.
31:02
So, here was the machine code looking Verilog after that's been, under median outputs this from its HDL will create this very grungy looking Verilog for you. We don't actually want to be reading that code. But what we do want to do is we want to hand it over to Coriolis 2.
31:27
Now, Coriolis 2 is the HDL automatic layout tool. And let's have a quick look here at an example program. Now, this is a very, very simple ALU which is very useful for what we're
31:44
doing. So, let me just quickly explain it. The top-line module has an op, which is a signal field. It has two input signals, A and B, and it has an output of bit width. So, these are HDL signals of width, width. And when we declare the class, we want to go, oh, we're declaring
32:02
this width 16. Fantastic. All right. So, now, there's an adder module and a subtractor module here. Let's have a quick look at those. So, the adder module has an A and a B as input, and it has O as output. And, oh, look, in combinatorial logic form, it adds A to B, and that's your output. Go figure. All right. And the subtract one, oh, look, that does a subtract of A from B.
32:26
So, what we then do is, depending on whether op is true or false, on the next clock cycle, the output will be set either to the results of the subtract or to the results of the add. Now, what I've found is that it is incredibly important to
32:45
view these things graphically. I didn't do gate level design or hardware things. I learned this on the fly. All right. So, here's your input A and B, which is part A and B are passed to
33:04
add and subtractor modules. The output's come from here, and then there's, depending on the op here, it will produce that output. Now, if we do proc opt synth.
33:22
Now, I don't normally do this, but I did want to show it to you because it shows you right down to the gate level. Now, what this has done is it has taken the cell library and gone down to individual cells. So, it's split out the bits of A and B,
33:48
received the output, and where is op? Yes, op goes into each individual mux here and selects one in each of the bits of A and B. And you don't normally see this kind of thing when you're
34:02
dealing with high level stuff. And then it goes into a flip flop to capture that output from the mux. So, it's stable for the, so it will be available for the next clock cycle. And then each output bit zero of each one gets put together and it goes into O, the output here. Okay. All right. Now, here's one I prepared earlier. All right.
34:28
Is this is what the actual chip looks like when it's done the layout. Okay. Whoops, I always get that wrong. And here's your individual transistors within the cells.
34:44
Okay. Now, in this particular program, what I did was, and this is a beautiful thing about Coriolis 2, I did a manual place of the adder on the left side and add a manual place of the subtractor on the right. And then I did a manual place on the individual components
35:08
of the cells in the muxes. And then, and from there, I asked it to do the routing, asked Coriolis to handle the routing. But all of this layout here was done,
35:26
I specified these locations of where I wanted this stuff to be in Python. And I specified in a Python program where I wanted the add to be, add block to be, and the subtract block to be.
35:43
Now, you can't do this kind of thing without having some kind of verification. So, what we did was a part of Coriolis 2, what it does is it extracts, once it's done this layout here, it re-extracts the netlist for you into a subset of VHDL. So, what we then did was
36:09
passed that VHDL over to a Cocotb simulation, which I've just got to find.
36:24
Right, Cocotb. Cocotb is similar to what we're doing inside the testing, except what it does is it takes where Numidian has its own simulator and you can run a side-by-side simulation of HDL versus some Python code. Cocotb does the exact same thing for Verilog and VHDL,
36:50
and so consequently, when we have this VHDL here, we can put it back into Cocotb and simulate it and, oh look, we can run the exact same JTAG tests that we did earlier,
37:07
including uploading over Wishbone, sending Wishbone commands. I apologize, it's quite hard to understand, but here's the command for read and write because that saves
37:22
a thing. So, we're writing the wishbone address here. We want to write to data address 00001, and then we want to write to memory and then read back again. So, we write the binary data here and then read back and then do an assert to make sure that
37:41
the result, standard Python assert, to make sure that the result comes back is what we expected. So, that's basically what we've been doing. I'm terribly sorry, I'm running out of time in the talk length, so just have to go briefly over these other things. One of the things that
38:04
we're also doing is implementing instructions. So, we're doing our own advanced instructions, adding those tests draft to the power instruction set because that's the funding that we got from NLAT to do this. And so, the one I'm currently doing is a discrete
38:22
cosine transform, which I start off from the original code. The best implementation I'll be able to find is a recursive one of Project Naoki. I then turned that into an iterative variant and then used Python iterators to express the triple loop that this is
38:48
in. DCT is usually expressed recursively. I created an iterative version that has three triple loops and then I created some Python generators which generate those so that we can
39:05
use them in the simulator and in the HDL and check the things that are going on. Anyway, very briefly, if you'd like to help, we do actually have funding available in several different areas. This is one serious computer science project,
39:21
mostly written in Python that NLNet have very kindly been supporting us in this endeavor. So, that's Coriolis 2. We have a script for an automated install of it, so you don't have to do the mess about trying to work out how to get it up and done. It will create a
39:43
Debian S root in Debian 10 for you. And again, that's the Chips for Makers website. If you want to do your own ASIC, he will help you and he's also a Python programmer. All right. So, yeah, if you would like to help his procedure. Thank you very much for your time.
40:13
Hello again. That is the end of the recorded portion of this talk session.
40:22
I would like to now invite Luke into the studio to answer any questions, though, as many of you in element will have noticed, Luke has been prolific in answering questions in Scout and providing extra resources and context to the talk. Thank you. That was
40:42
really informative. A little bit over my head just because I haven't done any embedded programming of any kind in my life, but wow. It's pretty heavy going. You just have to be extraordinarily patient with this level of detail. It's using Python to actually emulate and implement hardware.
41:06
I have a question, and this is super basic, but at least one other person who's attended this talk is in the same position. How do you get started with this?
41:29
It helps that I was using my first computer, H7, in 1977. So, I've been programming for 43 years, and I was messing about circuit boards, PCBs, when I was like 12,
41:51
things like that, soldering iron and all sorts of stuff. So, I kind of got the background, but you just make the decision. This is what I'm going to do. I had no idea what I was doing,
42:04
and to be honest, I still don't. But from the software engineering training, the rule at SD as an engineer was, before you start, always know what the answer is going to be.
42:29
How do you write yourself a tenor to look for what you're doing? And so, that's what I've been doing, and just very patiently drilling down fractal rabbit holes
42:47
in effect, one after the other, just very, very patiently, and learning what's needed as a go-along. That makes a lot of sense.
43:02
While we're waiting to see if anybody has a specific question in chat, I understand that this is like a rabbit hole in itself to ask about, but I have a security background, so whenever I end up using a tool, I end up having to do quite a lot of research into figuring out if it's secure or not. Package auditing is an entire nightmare.
43:25
Are you running entirely Libra software and hardware? Yes, yes. I've got a Versa ECP5 here, and one of our developers has a ULX3S.
43:42
The ECP5 was reverse engineered, so the tool chain for that is NextPNR-ECP5, and it's entirely Libra licensed. When we're even doing the FPGA testing,
44:03
we don't have to use installed Xilinx proprietary tools. Oh, right. Okay, that makes sense. I guess, kind of like your knowledge of hardware and processors, I assume that this is the kind of thing that you've just sort of built up and
44:25
accumulated over time, because I don't even know where I would begin to shift to that kind of tool chain. It's combining us as a series of projects, but it helps that I did
44:44
electronics when I was younger, and I've done embedded design, you know, so I've missed about with ARM boards. I've done reverse engineering. I did bring up on XDA developers in 2003, I was
45:04
using the Hiret or the GNU Hiret handheld reverse engineering tool to actually boot our own versions of Linux on Wint smartphones, and so the kinds of things that we need
45:22
for bootstrapping up the hardware, I know where I'm going, and it's a sort of a road map, so it's really strange. I just decided one day I was going to do this, but it turns out that everything that I'd done up to that point was relevant training for this project.
45:43
It's quite fortuitous. No, it makes sense, like there was a lot of transferable knowledge. For me, just from my level of experience and the kinds of things I've worked on, I have what I feel is like absolutely no transferable knowledge to get involved with this kind of work.
46:04
Well, I mean, later on, we'll actually have processors up and running on FPGAs, you know, big FPGAs, where we will need people to do security audits of the thing, you know, actually running programs and seeing if it's resistant to Spectre and Meltdown and blah,
46:21
blah, blah, et cetera, et cetera. But the nice thing is, by that point, you will actually be able to inspect the actual gate level running of the things and say, this is a problem here, and highlighting it for us and somebody can come along and fix it.
46:40
Can you imagine doing that with Intel? Yeah, if you've controlled everything about this piece of hardware end-to-end, you can audit it to a level of just like technical sophistication that you wouldn't otherwise be able to with a commercial board, for example.
47:01
Yeah, exactly. And the important thing about that is then that, did you hear that Supermicro got delisted from the NASDAQ stock exchange for being unable to prove the provenance of their components? I did actually read about that. Yeah, if they'd used our processor or used the techniques like it, they would have been
47:24
able to say, knock yourselves out, go and have a look at the, go and have a look at the HDL. And Huawei would have been able to take the US government to court over the removal of things because they'd be able to say, no, no, Mr. Trump, here's the under-SGR license,
47:43
you can actually expect the HDL. But you can't even do that with an Intel processor right now, or an AMD or an ARM or anything, because they licensed third-party macros. Intel will license about 60 different pieces of HDL for subcomponents, where even if you had
48:04
a customer come along with several million dollars saying, here's a wad of cash, I want to look at the source code, they'd hit a wall of 1000 lawyers from third-party IP. Right, and that impedes any further innovation in the space?
48:20
Basically, yes. Yeah, so we're actually sort of smashing open a whole stack of doors of, of what's it called, apathy. We're not just doing, you know, using this in Python, we're actually giving free software developers the opportunity to contribute to something that's
48:44
part of the future of computing. It's a fantastic project to be part of. Yeah, absolutely. It's pretty awesome. I'm delighted. We've got
49:00
€650,000 in funding from NLNet and from NGI Pointer. So if anybody wants to help out, they're more than welcome to do so. Yeah, we've essentially run out of time, and there will be a 10-minute break. But I feel like you've covered every possible question anybody could have possibly come up with. So thank you for giving this talk.
49:26
Is there, if people want to follow up, there's a breakout room available that they continue to, they can continue to ask questions in if you're available to answer anything else. But beyond that, it's because I feel like this is something people would want to do. Do you have a
49:44
preferred way of, preferred medium for communication? Like, can you be reached through Twitter or email or something? We're under audit conditions with NLNet, so private conversations are fine, no problem. But for technical discussions and etc, etc, we
50:00
have to use the IRC channel, which is logged, and mailing list on lists.libresoc.org. All resources and everything available, you just go to libresoc.org, or we're pretty high up on the search engines now. Just type in libresoc and you'll find us. All right. Thanks, Luke. That was an incredible talk. I learned a lot. I feel like it's going to
50:27
take a few months before it all settles in. And yeah, for everybody who is still currently in this room, we will now be taking a 10-minute break. I think we're at about the halfway mark
50:42
for the conference. Following that break, you will have a new session chair in this room. The next talk will be the spec you never knew you needed, and it'll be the next session chair's responsibility to give the pits for all of those. So thank you all for attending this talk. Once again, Luke, thank you for delivering it,
51:03
and I hope you have a good afternoon.