RISC-V is a new open, royalty-free instruction set specification from theUniversity of California, Berkeley that is finding its way into applicationsthat range from IoT to supercomputing. With the advent of RISC-V, hardwareimplementers are now able to build fully open-source CPUs. RISC-V distills over 30 years of RISC processor research at Berkeley andelsewhere into an extensible instruction set that can be fully customized. Inthis talk, we will discuss the goals of the RISC-V project and dig into theRISC-V instruction set. We will also give an overview of some popular open-source RISC-V hardware implementations as well as the RISC-V open-sourcesoftware stack.