Traditionally, the goal of digital hardware design has been to produce anASIC. Ideally one which works perfectly after the first tapeout. Tailoredtowards this goal are our development and testing processes: strictlyfollowing a V-model with separated development and verification teams, longdesign iterations and code which, once it's known to work, is never touchedagain. For people coming from the software world, this development approachlooks arcane. Where are all the sprints, the agile methods, the quickiterations? With FPGAs being on the rise and available in more and more cloud data centersand possibly bundled with our next Intel processor, we finally get the chanceto cheaply make mistakes in digital hardware designs: no more wasted tapeouts,just a new flashing of the FPGA is necessary to fix a bug. Join me in this talk for a look at development processes and tools. Where canwe build bridges between the software and hardware development world, andwhere do we have fundamentally different needs?